From db944ccc1e9d1750d1fac0616c0c6b654596a5d9 Mon Sep 17 00:00:00 2001 From: luowei Date: Thu, 27 Feb 2014 16:34:12 +0800 Subject: [PATCH] add rk3288 pinctrl dts code --- arch/arm/boot/dts/rk3288-pinctrl.dtsi | 813 ++++++++++++++++++ arch/arm/boot/dts/rk3288.dtsi | 1 + drivers/pinctrl/pinctrl-rockchip.c | 34 +- include/dt-bindings/pinctrl/rockchip-rk3188.h | 119 --- include/dt-bindings/pinctrl/rockchip-rk3288.h | 661 ++++++++++++++ include/dt-bindings/pinctrl/rockchip.h | 131 +++ 6 files changed, 1636 insertions(+), 123 deletions(-) create mode 100755 arch/arm/boot/dts/rk3288-pinctrl.dtsi mode change 100644 => 100755 arch/arm/boot/dts/rk3288.dtsi create mode 100755 include/dt-bindings/pinctrl/rockchip-rk3288.h diff --git a/arch/arm/boot/dts/rk3288-pinctrl.dtsi b/arch/arm/boot/dts/rk3288-pinctrl.dtsi new file mode 100755 index 000000000000..83bd7174a595 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-pinctrl.dtsi @@ -0,0 +1,813 @@ +#include +#include +#include +#include + +/ { + pinctrl@ff770000 { + compatible = "rockchip,rk3288-pinctrl"; + reg = <0xff770000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@ff750000 { + compatible = "rockchip,rk3288-gpio-bank0"; + reg = <0xff770000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff780000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff790000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 11>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff7a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7a0000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@ff7b0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7b0000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio5@ff7c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7c0000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio6@ff7d0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7d0000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio7@ff7e0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7e0000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio8@ff7f0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7f0000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio15: gpio15@ff7f2000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7f2000 0x100>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg_pull_up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg_pull_down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + gpio1_uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + uart0_cts: uart0-cts { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + uart0_rts: uart0-rts { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + }; + + gpio1_uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + uart1_cts: uart1-cts { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + uart1_rts: uart1-rts { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + }; + + gpio1_uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + /* no rts / cts for uart2 */ + }; + + gpio1_uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + uart3_cts: uart3-cts { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + uart3_rts: uart3-rts { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + }; + + gpio1_i2c0 { + i2c0_sda:i2c0-sda { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c0_scl:i2c0-scl { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c0_gpio: i2c0-gpio { + rockchip,pins = , ; + rockchip,drive = ; + }; + }; + + gpio1_i2c1 { + i2c1_sda:i2c1-sda { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c1_scl:i2c1-scl { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c1_gpio: i2c1-gpio { + rockchip,pins = , ; + rockchip,drive = ; + }; + }; + + gpio1_i2c2 { + i2c2_sda:i2c2-sda { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c2_scl:i2c2-scl { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c2_gpio: i2c2-gpio { + rockchip,pins = , ; + rockchip,drive = ; + }; + }; + + gpio1_i2c3 { + i2c3_sda:i2c3-sda { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c3_scl:i2c3-scl { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c3_gpio: i2c3-gpio { + rockchip,pins = , ; + rockchip,drive = ; + }; + }; + + gpio1_i2c4 { + i2c4_sda:i2c4-sda { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c4_scl:i2c4-scl { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c4_gpio: i2c4-gpio { + rockchip,pins = , ; + rockchip,drive = ; + }; + }; + + gpio1_i2c5 { + i2c5_sda:i2c5-sda { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c5_scl:i2c5-scl { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c5_gpio: i2c5-gpio { + rockchip,pins = , ; + rockchip,drive = ; + }; + }; + + gpio1_spi0 { + spi0_txd:spi0-txd { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi0_rxd:spi0-rxd { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi0_clk:spi0-clk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi0_cs0:spi0-cs0 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi0_cs1:spi0-cs1 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + }; + + gpio1_spi1 { + spi1_txd:spi1-txd { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi1_rxd:spi1-rxd { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi1_clk:spi1-clk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi1_cs0:spi1-cs0 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + }; + + gpio1_i2s { + + i2s_mclk:i2s-mclk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s_sclk:i2s-sclk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s_lrckrx:i2s-lrckrx { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s_lrcktx:i2s-lrcktx { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s_sdo0:i2s-sdo0 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s_sdo1:i2s-sdo1 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s_sdo2:i2s-sdo2 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s_sdo3:i2s-sdo3 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s_sdi:i2s-sdi { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s_gpio: i2s-gpio { + rockchip,pins = , + , + , + , + , + , + , + , + ; + + rockchip,drive = ; + }; + }; + + gpio1_lcdc0 { + lcdc0_lcdc:lcdc0-lcdc { + rockchip,pins = + , + , + , + ; + rockchip,pull = ; + rockchip,drive = ; + }; + + lcdc0_gpio:lcdc0-gpio { + rockchip,pins = + , + , + , + ; + rockchip,pull = ; + rockchip,drive = ; + + }; + + }; + + gpio1_spdif { + spdif_tx: spdif-tx { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + }; + + gpio3_pwm { + pwm0_pin:pwm0 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + + pwm1_pin:pwm1 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + + pwm2_pin:pwm2 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + + pwm3_pin:pwm3 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + }; + + gpio3_emmc0 { + emmc0_clk: emmc0-clk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + emmc0_cmd: emmc0-cmd { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + emmc0_rstnout: emmc0-rstnout { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + + emmc0_pwr: emmc0-pwr { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + emmc0_bus1: emmc0-bus-width1 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + emmc0_bus4: emmc0-bus-width4 { + rockchip,pins = , + , + , + ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + }; + + + gpio3_sdmmc0 { + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + sdmmc0_dectn: sdmmc0-dectn{ + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + + sdmmc0_bus1: sdmmc0-bus-width1 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + sdmmc0_bus4: sdmmc0-bus-width4 { + rockchip,pins = , + , + , + ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + }; + + gps { + gps_mag:gps-mag { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + gps_sig:gps-sig { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + + gps_rfclk:gps-rfclk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + }; + + vol_domain { + ap0_vcc:ap0-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + ap1_vcc:ap1-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + cif_vcc:cif-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash_vcc:flash-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + vccio0_vcc:vccio0-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + vccio1_vcc:vccio1-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + lcdc0_vcc:lcdc0-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + lcdc1_vcc:lcdc1-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + }; + + //to add + }; +}; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi old mode 100644 new mode 100755 index bd9d6558459a..6469a084be74 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1,5 +1,6 @@ #include #include "skeleton.dtsi" +#include "rk3288-pinctrl.dtsi" / { compatible = "rockchip,rk3288"; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 34850f6d688f..d99cf24b046c 100755 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -40,8 +40,6 @@ #include #include #include -#include - #include #include @@ -63,7 +61,7 @@ /* GPIO control registers */ #define GPIO_SWPORT_DR 0x00 #define GPIO_SWPORT_DDR 0x04 -#define GPIO_INTEN 0x30 +#define GPIO_INTEN 0x30 #define GPIO_INTMASK 0x34 #define GPIO_INTTYPE_LEVEL 0x38 #define GPIO_INT_POLARITY 0x3c @@ -78,6 +76,7 @@ enum rockchip_pinctrl_type { RK2928, RK3066B, RK3188, + RK3288, }; enum rockchip_pin_bank_type { @@ -2294,9 +2293,34 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .label = "RK3188-GPIO", .type = RK3188, .mux_offset = 0x60, - .pull_calc_reg = rk3188_calc_pull_reg_and_bit, + .pull_calc_reg = rk3188_calc_pull_reg_and_bit, +}; + + +static struct rockchip_pin_bank rk3288_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), + PIN_BANK(4, 32, "gpio4"), + PIN_BANK(5, 32, "gpio5"), + PIN_BANK(6, 32, "gpio6"), + PIN_BANK(7, 32, "gpio7"), + PIN_BANK(8, 32, "gpio8"), + + + PIN_BANK(15, 32, "gpio15"),//virtual bank +}; + +static struct rockchip_pin_ctrl rk3288_pin_ctrl = { + .pin_banks = rk3288_pin_banks, + .nr_banks = ARRAY_SIZE(rk3288_pin_banks), + .label = "RK3288-GPIO", + .type = RK3288, + .mux_offset = 0x60, }; + static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rk2928-pinctrl", .data = (void *)&rk2928_pin_ctrl }, @@ -2306,6 +2330,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3066b_pin_ctrl }, { .compatible = "rockchip,rk3188-pinctrl", .data = (void *)&rk3188_pin_ctrl }, + { .compatible = "rockchip,rk3288-pinctrl", + .data = (void *)&rk3288_pin_ctrl }, {}, }; MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); diff --git a/include/dt-bindings/pinctrl/rockchip-rk3188.h b/include/dt-bindings/pinctrl/rockchip-rk3188.h index f806dbce3c94..0b4a142471e6 100755 --- a/include/dt-bindings/pinctrl/rockchip-rk3188.h +++ b/include/dt-bindings/pinctrl/rockchip-rk3188.h @@ -451,123 +451,4 @@ #define JTAG_TMS 0x3d62 #define HOST_DRV_VBUS 0x3d63 -/*special virtual pin for vcc domain setting*/ -#define VIRTUAL_PIN_FOR_AP0_VCC 0xfA00 -#define VIRTUAL_PIN_FOR_AP1_VCC 0xfA10 -#define VIRTUAL_PIN_FOR_CIF_VCC 0xfA20 -#define VIRTUAL_PIN_FOR_FLASH_VCC 0xfA30 -#define VIRTUAL_PIN_FOR_VCCIO0_VCC 0xfA40 -#define VIRTUAL_PIN_FOR_VCCIO1_VCC 0xfA50 -#define VIRTUAL_PIN_FOR_LCDC0_VCC 0xfA60 -#define VIRTUAL_PIN_FOR_LCDC1_VCC 0xfA70 - -#define TYPE_PULL_REG 0x01 -#define TYPE_VOL_REG 0x02 -#define TYPE_DRV_REG 0x03 -#define TYPE_TRI_REG 0x04 - -#define RK3188_GRF_IO_CON0 0xf4 -#define RK3188_GRF_IO_CON1 0xf8 -#define RK3188_GRF_IO_CON2 0xfc -#define RK3188_GRF_IO_CON3 0x100 -#define RK3188_GRF_IO_CON4 0x104 - - -#define RK2928_PULL_OFFSET 0x118 -#define RK2928_PULL_PINS_PER_REG 16 -#define RK2928_PULL_BANK_STRIDE 8 - -#define RK3188_PULL_BITS_PER_PIN 2 -#define RK3188_PULL_PINS_PER_REG 8 -#define RK3188_PULL_BANK_STRIDE 16 - - -/*warning:don not chang the following value*/ -#define VALUE_PULL_DISABLE 0 -#define VALUE_PULL_UP 1 -#define VALUE_PULL_DOWN 2 -#define VALUE_PULL_DEFAULT 3 - -#define VALUE_VOL_DEFAULT 0 -#define VALUE_VOL_3V3 0 -#define VALUE_VOL_1V8 1 - -#define VALUE_DRV_DEFAULT 0 -#define VALUE_DRV_2MA 0 -#define VALUE_DRV_4MA 1 -#define VALUE_DRV_8MA 2 -#define VALUE_DRV_12MA 3 - -#define VALUE_TRI_DEFAULT 0 -#define VALUE_TRI_FALSE 0 -#define VALUE_TRI_TRUE 1 - - -/* - * pin config bit field definitions - * - * pull-up: 1..0 (2) - * voltage: 3..2 (2) - * drive: 5..4 (2) - * trisiate: 7..6 (2) - * - * MSB of each field is presence bit for the config. - */ -#define PULL_SHIFT 0 -#define PULL_PRESENT (1 << 2) -#define VOL_SHIFT 3 -#define VOL_PRESENT (1 << 5) -#define DRV_SHIFT 6 -#define DRV_PRESENT (1 << 8) -#define TRI_SHIFT 9 -#define TRI_PRESENT (1 << 11) - -#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x3) -#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x3) -#define CONFIG_TO_DRV(c) ((c) >> DRV_SHIFT & 0x3) -#define CONFIG_TO_TRI(c) ((c) >> TRI_SHIFT & 0x3) - - -#define MAX_NUM_CONFIGS 4 -#define POS_PULL 0 -#define POS_VOL 1 -#define POS_DRV 2 -#define POS_TRI 3 - - -#define GPIO_A0 0 -#define GPIO_A1 1 -#define GPIO_A2 2 -#define GPIO_A3 3 -#define GPIO_A4 4 -#define GPIO_A5 5 -#define GPIO_A6 6 -#define GPIO_A7 7 -#define GPIO_B0 8 -#define GPIO_B1 9 -#define GPIO_B2 10 -#define GPIO_B3 11 -#define GPIO_B4 12 -#define GPIO_B5 13 -#define GPIO_B6 14 -#define GPIO_B7 15 -#define GPIO_C0 16 -#define GPIO_C1 17 -#define GPIO_C2 18 -#define GPIO_C3 19 -#define GPIO_C4 20 -#define GPIO_C5 21 -#define GPIO_C6 22 -#define GPIO_C7 23 -#define GPIO_D0 24 -#define GPIO_D1 25 -#define GPIO_D2 26 -#define GPIO_D3 27 -#define GPIO_D4 28 -#define GPIO_D5 29 -#define GPIO_D6 30 -#define GPIO_D7 31 - -#define FUNC_TO_GPIO(m) ((m) & 0xfff0) - #endif diff --git a/include/dt-bindings/pinctrl/rockchip-rk3288.h b/include/dt-bindings/pinctrl/rockchip-rk3288.h new file mode 100755 index 000000000000..23137fffe3a4 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk3288.h @@ -0,0 +1,661 @@ +/* + * Header providing constants for Rockchip pinctrl bindings. + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3288_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3288_H__ + +/* GPIO0_A */ +#define GPIO0_A0 0x0a00 +#define GLOBAL_PWROFF 0x0a01 + +#define GPIO0_A1 0x0a10 +#define DDRIO_PWROFF 0x0a11 + +#define GPIO0_A2 0x0a20 +#define DDR0_RETENTION 0x0a21 + +#define GPIO0_A3 0x0a30 +#define DDR1_RETENTION 0x0a31 + + +/* GPIO0_B */ +#define GPIO0_B0 0x0b00 +#define TSADC_INT 0x0b01 + +#define GPIO0_B5 0x0b50 +#define CLK_27M 0x0b51 + +#define GPIO0_B7 0x0b70 +#define I2C0PMU_SDA 0x0b71 + + +/* GPIO0_C */ +#define GPIO0_C0 0x0c00 +#define I2C0PMU_SCL 0x0c01 + +#define GPIO0_C1 0x0c10 +#define TEST_CLKOUT 0x0c11 +#define CLKT1_27M 0x0c12 + + +/* GPIO0_D */ +#define GPIO0_D0 0x0d00 +#define LCDC0_HSYNC_GPIO0D 0x0d01 + +#define GPIO0_D1 0x0d10 +#define LCDC0_VSYNC_GPIO0D 0x0d11 + +#define GPIO0_D2 0x0d20 +#define LCDC0_DEN_GPIO0D 0x0d21 + +#define GPIO0_D3 0x0d30 +#define LCDC0_DCLK_GPIO0D 0x0d31 + + +/* GPIO1_A */ +/* GPIO1_B */ +/* GPIO1_C */ +/* GPIO1_D */ +#define GPIO1_D0 0x1d00 +#define LCDC0_HSYNC_GPIO1D 0x1d01 + +#define GPIO1_D1 0x1d10 +#define LCDC0_VSYNC_GPIO1D 0x1d11 + +#define GPIO1_D2 0x1d20 +#define LCDC0_DEN_GPIO1D 0x1d21 + +#define GPIO1_D3 0x1d30 +#define LCDC0_DCLK_GPIO1D 0x1d31 + + +/* GPIO2_A */ +#define GPIO2_A0 0x2a00 +#define CIF_DATA2 0x2a01 +#define HOST_DIN0 0x2a02 +#define HSADC_DATA0 0x2a03 + +#define GPIO2_A1 0x2a10 +#define CIF_DATA3 0x2a11 +#define HOST_DIN1 0x2a12 +#define HSADC_DATA1 0x2a13 + +#define GPIO2_A2 0x2a20 +#define CIF_DATA4 0x2a21 +#define HOST_DIN2 0x2a22 +#define HSADC_DATA2 0x2a23 + +#define GPIO2_A3 0x2a30 +#define CIF_DATA5 0x2a31 +#define HOST_DIN3 0x2a32 +#define HSADC_DATA3 0x2a33 + +#define GPIO2_A4 0x2a40 +#define CIF_DATA6 0x2a41 +#define HOST_CKINP 0x2a42 +#define HSADC_DATA4 0x2a43 + +#define GPIO2_A5 0x2a50 +#define CIF_DATA7 0x2a51 +#define HOST_CKINN 0x2a52 +#define HSADC_DATA5 0x2a53 + +#define GPIO2_A6 0x2a60 +#define CIF_DATA8 0x2a61 +#define HOST_DIN4 0x2a62 +#define HSADC_DATA6 0x2a63 + +#define GPIO2_A7 0x2a70 +#define CIF_DATA9 0x2a71 +#define HOST_DIN5 0x2a72 +#define HSADC_DATA7 0x2a73 + + +/* GPIO2_B */ +#define GPIO2_B0 0x2b00 +#define CIF_VSYNC 0x2b01 +#define HOST_DIN6 0x2b02 +#define HSADCTS_SYNC 0x2b03 + +#define GPIO2_B1 0x2b10 +#define CIF_HREF 0x2b11 +#define HOST_DIN7 0x2b12 +#define HSADCTS_VALID 0x2b13 + +#define GPIO2_B2 0x2b20 +#define CIF_CLKIN 0x2b21 +#define HOST_WKACK 0x2b22 +#define GPS_CLK 0x2b23 + +#define GPIO2_B3 0x2b30 +#define CIF_CLKOUT 0x2b31 +#define HOST_WKREQ 0x2b32 +#define HSADCTS_FAIL 0x2b33 + +#define GPIO2_B4 0x2b40 +#define CIF_DATA0 0x2b41 + +#define GPIO2_B5 0x2b50 +#define CIF_DATA1 0x2b51 + +#define GPIO2_B6 0x2b60 +#define CIF_DATA10 0x2b61 + +#define GPIO2_B7 0x2b70 +#define CIF_DATA11 0x2b71 + + +/* GPIO2_C */ +#define GPIO2_C0 0x2c00 +#define I2C3CAM_SCL 0x2c01 + +#define GPIO2_C1 0x2c10 +#define I2C3CAM_SDA 0x2c11 + + +/* GPIO2_D */ +/* GPIO3_A */ +#define GPIO3_A0 0x3a00 +#define FLASH0_DATA0 0x3a01 +#define EMMC_DATA0 0x3a02 + +#define GPIO3_A1 0x3a10 +#define FLASH0_DATA1 0x3a11 +#define EMMC_DATA1 0x3a12 + +#define GPIO3_A2 0x3a20 +#define FLASH0_DATA2 0x3a21 +#define EMMC_DATA2 0x3a22 + +#define GPIO3_A3 0x3a30 +#define FLASH0_DATA3 0x3a31 +#define EMMC_DATA3 0x3a32 + +#define GPIO3_A4 0x3a40 +#define FLASH0_DATA4 0x3a41 +#define EMMC_DATA4 0x3a42 + +#define GPIO3_A5 0x3a50 +#define FLASH0_DATA5 0x3a51 +#define EMMC_DATA5 0x3a52 + +#define GPIO3_A6 0x3a60 +#define FLASH0_DATA6 0x3a61 +#define EMMC_DATA6 0x3a62 + +#define GPIO3_A7 0x3a70 +#define FLASH0_DATA7 0x3a71 +#define EMMC_DATA7 0x3a72 + + +/* GPIO3_B */ +#define GPIO3_B0 0x3b00 +#define FLASH0_RDY 0x3b01 + +#define GPIO3_B1 0x3b10 +#define FLASH0_WP 0x3b11 +#define EMMC_PWREN 0x3b12 + +#define GPIO3_B2 0x3b20 +#define FLASH0_RDN 0x3b21 + +#define GPIO3_B3 0x3b30 +#define FLASH0_ALE 0x3b31 + +#define GPIO3_B4 0x3b40 +#define FLASH0_CLE 0x3b41 + +#define GPIO3_B5 0x3b50 +#define FLASH0_WRN 0x3b51 + +#define GPIO3_B6 0x3b60 +#define FLASH0_CSN0 0x3b61 + +#define GPIO3_B7 0x3b70 +#define FLASH0_CSN1 0x3b71 + + +/* GPIO3_C */ +#define GPIO3_C0 0x3c00 +#define FLASH0_CSN2 0x3c01 +#define EMMC_CMD 0x3c02 + +#define GPIO3_C1 0x3c10 +#define FLASH0_CSN3 0x3c11 +#define EMMC_RSTNOUT 0x3c12 + +#define GPIO3_C2 0x3c20 +#define FLASH0_DQS 0x3c21 +#define EMMC_CLKOUT 0x3c22 + + +/* GPIO3_D */ +#define GPIO3_D0 0x3d00 +#define FLASH1_DATA0 0x3d01 +#define HOST_DOUT0 0x3d02 +#define MAC_TXD2 0x3d03 +#define SDIO1_DATA0 0x3d04 + +#define GPIO3_D1 0x3d10 +#define FLASH1_DATA1 0x3d11 +#define HOST_DOUT1 0x3d12 +#define MAC_TXD3 0x3d13 +#define SDIO1_DATA1 0x3d14 + +#define GPIO3_D2 0x3d20 +#define FLASH1_DATA2 0x3d21 +#define HOST_DOUT2 0x3d22 +#define MAC_RXD2 0x3d23 +#define SDIO1_DATA2 0x3d24 + +#define GPIO3_D3 0x3d30 +#define FLASH1_DATA3 0x3d31 +#define HOST_DOUT3 0x3d32 +#define MAC_RXD3 0x3d33 +#define SDIO1_DATA3 0x3d34 + +#define GPIO3_D4 0x3d40 +#define FLASH1_DATA4 0x3d41 +#define HOST_DOUT4 0x3d42 +#define MAC_TXD0 0x3d43 +#define SDIO1_DETECTN 0x3d44 + +#define GPIO3_D5 0x3d50 +#define FLASH1_DATA5 0x3d51 +#define HOST_DOUT5 0x3d52 +#define MAC_TXD1 0x3d53 +#define SDIO1_WRPRT 0x3d54 + +#define GPIO3_D6 0x3d60 +#define FLASH1_DATA6 0x3d61 +#define HOST_DOUT6 0x3d62 +#define MAC_RXD0 0x3d63 +#define SDIO1_BKPWR 0x3d64 + +#define GPIO3_D7 0x3d70 +#define FLASH1_DATA7 0x3d71 +#define HOST_DOUT7 0x3d72 +#define MAC_RXD1 0x3d73 +#define SDIO1_INTN 0x3d74 + + +/* GPIO4_A */ +#define GPIO4_A0 0x4a00 +#define FLASH1_RDY 0x4a01 +#define HOST_CKOUTP 0x4a02 +#define MAC_MDC 0x4a03 + +#define GPIO4_A1 0x4a10 +#define FLASH1_WP 0x4a11 +#define HOST_CKOUTN 0x4a12 +#define MAC_RXDV 0x4a13 +#define FLASH0_CSN4 0x4a14 + +#define GPIO4_A2 0x4a20 +#define FLASH1_RDN 0x4a21 +#define HOST_DOUT8 0x4a22 +#define MAC_RXER 0x4a23 +#define FLASH0_CSN5 0x4a24 + +#define GPIO4_A3 0x4a30 +#define FLASH1_ALE 0x4a31 +#define HOST_DOUT9 0x4a32 +#define MAC_CLK 0x4a33 +#define FLASH0_CSN6 0x4a34 + +#define GPIO4_A4 0x4a40 +#define FLASH1_CLE 0x4a41 +#define HOST_DOUT10 0x4a42 +#define MAC_TXEN 0x4a43 +#define FLASH0_CSN7 0x4a44 + +#define GPIO4_A5 0x4a50 +#define FLASH1_WRN 0x4a51 +#define HOST_DOUT11 0x4a52 +#define MAC_MDIO 0x4a53 + +#define GPIO4_A6 0x4a60 +#define FLASH1_CSN0 0x4a61 +#define HOST_DOUT12 0x4a62 +#define MAC_RXCLK 0x4a63 +#define SDIO1_CMD 0x4a64 + +#define GPIO4_A7 0x4a70 +#define FLASH1_CSN1 0x4a71 +#define HOST_DOUT13 0x4a72 +#define MAC_CRS 0x4a73 +#define SDIO1_CLKOUT 0x4a74 + + +/* GPIO4_B */ +#define GPIO4_B0 0x4b00 +#define FLASH1_DQS 0x4b01 +#define HOST_DOUT14 0x4b02 +#define MAC_COL 0x4b03 +#define FLASH1_CSN3 0x4b04 + +#define GPIO4_B1 0x4b10 +#define FLASH1_CSN2 0x4b11 +#define HOST_DOUT15 0x4b12 +#define MAC_TXCLK 0x4b13 +#define SDIO1_PWREN 0x4b14 + + +/* GPIO4_C */ +#define GPIO4_C0 0x4c00 +#define UART0BT_SIN 0x4c01 + +#define GPIO4_C1 0x4c10 +#define UART0BT_SOUT 0x4c11 + +#define GPIO4_C2 0x4c20 +#define UART0BT_CTSN 0x4c21 + +#define GPIO4_C3 0x4c30 +#define UART0BT_RTSN 0x4c31 + +#define GPIO4_C4 0x4c40 +#define SDIO0_DATA0 0x4c41 + +#define GPIO4_C5 0x4c50 +#define SDIO0_DATA1 0x4c51 + +#define GPIO4_C6 0x4c60 +#define SDIO0_DATA2 0x4c61 + +#define GPIO4_C7 0x4c70 +#define SDIO0_DATA3 0x4c71 + + +/* GPIO4_D */ +#define GPIO4_D0 0x4d00 +#define SDIO0_CMD 0x4d01 + +#define GPIO4_D1 0x4d10 +#define SDIO0_CLKOUT 0x4d11 + +#define GPIO4_D2 0x4d20 +#define SDIO0_DETECTN 0x4d21 + +#define GPIO4_D3 0x4d30 +#define SDIO0_WRPRT 0x4d31 + +#define GPIO4_D4 0x4d40 +#define SDIO0_PWREN 0x4d41 + +#define GPIO4_D5 0x4d50 +#define SDIO0_BKPWR 0x4d51 + +#define GPIO4_D6 0x4d60 +#define SDIO0_INTN 0x4d61 + + +/* GPIO5_A */ +/* GPIO5_B */ +#define GPIO5_B0 0x5b00 +#define UART1BB_SIN 0x5b01 +#define TS0_DATA0 0x5b02 + +#define GPIO5_B1 0x5b10 +#define UART1BB_SOUT 0x5b11 +#define TS0_DATA1 0x5b12 + +#define GPIO5_B2 0x5b20 +#define UART1BB_CTSN 0x5b21 +#define TS0_DATA2 0x5b22 + +#define GPIO5_B3 0x5b30 +#define UART1BB_RTSN 0x5b31 +#define TS0_DATA3 0x5b32 + +#define GPIO5_B4 0x5b40 +#define SPI0_CLK 0x5b41 +#define TS0_DATA4 0x5b42 +#define UART4EXP_CTSN 0x5b43 + +#define GPIO5_B5 0x5b50 +#define SPI0_CS0 0x5b51 +#define TS0_DATA5 0x5b52 +#define UART4EXP_RTSN 0x5b53 + +#define GPIO5_B6 0x5b60 +#define SPI0_TXD 0x5b61 +#define TS0_DATA6 0x5b62 +#define UART4EXP_SOUT 0x5b63 + +#define GPIO5_B7 0x5b70 +#define SPI0_RXD 0x5b71 +#define TS0_DATA7 0x5b72 +#define UART4EXP_SIN 0x5b73 + + +/* GPIO5_C */ +#define GPIO5_C0 0x5c00 +#define SPI0_CS1 0x5c01 +#define TS0_SYNC 0x5c02 + +#define GPIO5_C1 0x5c10 +#define TS0_VALID 0x5c11 + +#define GPIO5_C2 0x5c20 +#define TS0_CLK 0x5c21 + +#define GPIO5_C3 0x5c30 +#define TS0_ERR 0x5c31 + + +/* GPIO5_D */ +/* GPIO6_A */ +#define GPIO6_A0 0x6a00 +#define I2S_SCLK 0x6a01 + +#define GPIO6_A1 0x6a10 +#define I2S_LRCKRX 0x6a11 + +#define GPIO6_A2 0x6a20 +#define I2S_LRCKTX 0x6a21 + +#define GPIO6_A3 0x6a30 +#define I2S_SDI 0x6a31 + +#define GPIO6_A4 0x6a40 +#define I2S_SDO0 0x6a41 + +#define GPIO6_A5 0x6a50 +#define I2S_SDO1 0x6a51 + +#define GPIO6_A6 0x6a60 +#define I2S_SDO2 0x6a61 + +#define GPIO6_A7 0x6a70 +#define I2S_SDO3 0x6a71 + + +/* GPIO6_B */ +#define GPIO6_B0 0x6b00 +#define I2S_CLK 0x6b01 + +#define GPIO6_B1 0x6b10 +#define I2C2AUDIO_SDA 0x6b11 + +#define GPIO6_B2 0x6b20 +#define I2C2AUDIO_SCL 0x6b21 + +#define GPIO6_B3 0x6b30 +#define SPDIF_TX 0x6b31 + + +/* GPIO6_C */ +#define GPIO6_C0 0x6c00 +#define SDMMC0_DATA0 0x6c01 +#define JTAG_TMS 0x6c02 + +#define GPIO6_C1 0x6c10 +#define SDMMC0_DATA1 0x6c11 +#define JTAG_TRSTN 0x6c12 + +#define GPIO6_C2 0x6c20 +#define SDMMC0_DATA2 0x6c21 +#define JTAG_TDI 0x6c22 + +#define GPIO6_C3 0x6c30 +#define SDMMC0_DATA3 0x6c31 +#define JTAG_TCK 0x6c32 + +#define GPIO6_C4 0x6c40 +#define SDMMC0_CLKOUT 0x6c41 +#define JTAG_TDO 0x6c42 + +#define GPIO6_C5 0x6c50 +#define SDMMC0_CMD 0x6c51 + +#define GPIO6_C6 0x6c60 +#define SDMMC0_DECTN 0x6c61 + + +/* GPIO6_D */ +/* GPIO7_A */ +#define GPIO7_A0 0x7a00 +#define PWM0 0x7a01 +#define VOP0_PWM 0x7a02 +#define VOP1_PWM 0x7a03 + +#define GPIO7_A1 0x7a10 +#define PWM1 0x7a11 + +#define GPIO7_A7 0x7a70 +#define UART3GPS_SIN 0x7a71 +#define GPS_MAG 0x7a72 +#define HSADCT1_DATA0 0x7a73 + + +/* GPIO7_B */ +#define GPIO7_B0 0x7b00 +#define UART3GPS_SOUT 0x7b01 +#define GPS_SIG 0x7b02 +#define HSADCT1_DATA1 0x7b03 + +#define GPIO7_B1 0x7b10 +#define UART3GPS_CTSN 0x7b11 +#define GPS_RFCLK 0x7b12 +#define GPST1_CLK 0x7b13 + +#define GPIO7_B2 0x7b20 +#define UART3GPS_RTSN 0x7b21 +#define USB_DRVVBUS0 0x7b22 + +#define GPIO7_B3 0x7b30 +#define USB_DRVVBUS1 0x7b31 +#define EDP_HOTPLUG 0x7b32 + +#define GPIO7_B4 0x7b40 +#define ISP_SHUTTEREN 0x7b41 +#define SPI1_CLK 0x7b42 + +#define GPIO7_B5 0x7b50 +#define ISP_FLASHTRIGOUTSPI1_CS0 0x7b51 +#define SPI1_CS0 0x7b52 + +#define GPIO7_B6 0x7b60 +#define ISP_PRELIGHTTRIGSPI1_RXD 0x7b61 +#define SPI1_RXD 0x7b62 + +#define GPIO7_B7 0x7b70 +#define ISP_SHUTTERTRIG 0x7b71 +#define SPI1_TXD 0x7b72 + + +/* GPIO7_C */ +#define GPIO7_C0 0x7c00 +#define ISP_FLASHTRIGIN 0x7c01 +#define EDPHDMI_CECINOUTRESERVED 0x7c02 + +#define GPIO7_C1 0x7c10 +#define I2C4TP_SDA 0x7c11 + +#define GPIO7_C2 0x7c20 +#define I2C4TP_SCL 0x7c21 + +#define GPIO7_C3 0x7c30 +#define I2C5HDMI_SDA 0x7c31 +#define EDPHDMII2C_SDA 0x7c32 + +#define GPIO7_C4 0x7c40 +#define I2C5HDMI_SCL 0x7c41 +#define EDPHDMII2C_SCL 0x7c42 + +#define GPIO7_C6 0x7c60 +#define UART2DBG_SIN 0x7c61 +#define UART2DBG_SIRIN 0x7c62 +#define PWM2 0x7c63 + +#define GPIO7_C7 0x7c70 +#define UART2DBG_SOUT 0x7c71 +#define UART2DBG_SIROUT 0x7c72 +#define PWM3 0x7c73 +#define EDPHDMI_CECINOUT 0x7c74 + + +/* GPIO7_D */ +/* GPIO8_A */ +#define GPIO8_A0 0x8a00 +#define PS2_CLK 0x8a01 +#define SC_VCC18V 0x8a02 + +#define GPIO8_A1 0x8a10 +#define PS2_DATA 0x8a11 +#define SC_VCC33V 0x8a12 + +#define GPIO8_A2 0x8a20 +#define SC_DETECTT1 0x8a21 + +#define GPIO8_A3 0x8a30 +#define SPI2_CS1 0x8a31 +#define SC_IOT1 0x8a32 + +#define GPIO8_A4 0x8a40 +#define I2C1SENSOR_SDA 0x8a41 +#define SC_RST_GPIO8A 0x8a42 + +#define GPIO8_A5 0x8a50 +#define I2C1SENSOR_SCL 0x8a51 +#define SC_CLK_GPIO8A 0x8a52 + +#define GPIO8_A6 0x8a60 +#define SPI2_CLK 0x8a61 +#define SC_IO 0x8a62 + +#define GPIO8_A7 0x8a70 +#define SPI2_CS0 0x8a71 +#define SC_DETECT 0x8a72 + + +/* GPIO8_B */ +#define GPIO8_B0 0x8b00 +#define SPI2_RXD 0x8b01 +#define SC_RST_GPIO8B 0x8b02 + +#define GPIO8_B1 0x8b10 +#define SPI2_TXD 0x8b11 +#define SC_CLK_GPIO8B 0x8b12 + + +/* GPIO8_C */ +/* GPIO8_D */ + + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index cd5788be82ce..1550654d620e 100755 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -23,10 +23,141 @@ #define RK_GPIO2 2 #define RK_GPIO3 3 #define RK_GPIO4 4 +#define RK_GPIO5 5 #define RK_GPIO6 6 +#define RK_GPIO7 7 +#define RK_GPIO8 8 + #define RK_FUNC_GPIO 0 #define RK_FUNC_1 1 #define RK_FUNC_2 2 +#define RK_FUNC_3 3 +#define RK_FUNC_4 4 +#define RK_FUNC_5 5 +#define RK_FUNC_6 6 +#define RK_FUNC_7 7 + + + +/*special virtual pin for vcc domain setting*/ +#define VIRTUAL_PIN_FOR_AP0_VCC 0xfA00 +#define VIRTUAL_PIN_FOR_AP1_VCC 0xfA10 +#define VIRTUAL_PIN_FOR_CIF_VCC 0xfA20 +#define VIRTUAL_PIN_FOR_FLASH_VCC 0xfA30 +#define VIRTUAL_PIN_FOR_VCCIO0_VCC 0xfA40 +#define VIRTUAL_PIN_FOR_VCCIO1_VCC 0xfA50 +#define VIRTUAL_PIN_FOR_LCDC0_VCC 0xfA60 +#define VIRTUAL_PIN_FOR_LCDC1_VCC 0xfA70 + +#define TYPE_PULL_REG 0x01 +#define TYPE_VOL_REG 0x02 +#define TYPE_DRV_REG 0x03 +#define TYPE_TRI_REG 0x04 + +#define RK3188_GRF_IO_CON0 0xf4 +#define RK3188_GRF_IO_CON1 0xf8 +#define RK3188_GRF_IO_CON2 0xfc +#define RK3188_GRF_IO_CON3 0x100 +#define RK3188_GRF_IO_CON4 0x104 + + +#define RK2928_PULL_OFFSET 0x118 +#define RK2928_PULL_PINS_PER_REG 16 +#define RK2928_PULL_BANK_STRIDE 8 + +#define RK3188_PULL_BITS_PER_PIN 2 +#define RK3188_PULL_PINS_PER_REG 8 +#define RK3188_PULL_BANK_STRIDE 16 + + +/*warning:don not chang the following value*/ +#define VALUE_PULL_DISABLE 0 +#define VALUE_PULL_UP 1 +#define VALUE_PULL_DOWN 2 +#define VALUE_PULL_DEFAULT 3 + +#define VALUE_VOL_DEFAULT 0 +#define VALUE_VOL_3V3 0 +#define VALUE_VOL_1V8 1 + +#define VALUE_DRV_DEFAULT 0 +#define VALUE_DRV_2MA 0 +#define VALUE_DRV_4MA 1 +#define VALUE_DRV_8MA 2 +#define VALUE_DRV_12MA 3 + +#define VALUE_TRI_DEFAULT 0 +#define VALUE_TRI_FALSE 0 +#define VALUE_TRI_TRUE 1 + + +/* + * pin config bit field definitions + * + * pull-up: 1..0 (2) + * voltage: 3..2 (2) + * drive: 5..4 (2) + * trisiate: 7..6 (2) + * + * MSB of each field is presence bit for the config. + */ +#define PULL_SHIFT 0 +#define PULL_PRESENT (1 << 2) +#define VOL_SHIFT 3 +#define VOL_PRESENT (1 << 5) +#define DRV_SHIFT 6 +#define DRV_PRESENT (1 << 8) +#define TRI_SHIFT 9 +#define TRI_PRESENT (1 << 11) + +#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x3) +#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x3) +#define CONFIG_TO_DRV(c) ((c) >> DRV_SHIFT & 0x3) +#define CONFIG_TO_TRI(c) ((c) >> TRI_SHIFT & 0x3) + + +#define MAX_NUM_CONFIGS 4 +#define POS_PULL 0 +#define POS_VOL 1 +#define POS_DRV 2 +#define POS_TRI 3 + + +#define GPIO_A0 0 +#define GPIO_A1 1 +#define GPIO_A2 2 +#define GPIO_A3 3 +#define GPIO_A4 4 +#define GPIO_A5 5 +#define GPIO_A6 6 +#define GPIO_A7 7 +#define GPIO_B0 8 +#define GPIO_B1 9 +#define GPIO_B2 10 +#define GPIO_B3 11 +#define GPIO_B4 12 +#define GPIO_B5 13 +#define GPIO_B6 14 +#define GPIO_B7 15 +#define GPIO_C0 16 +#define GPIO_C1 17 +#define GPIO_C2 18 +#define GPIO_C3 19 +#define GPIO_C4 20 +#define GPIO_C5 21 +#define GPIO_C6 22 +#define GPIO_C7 23 +#define GPIO_D0 24 +#define GPIO_D1 25 +#define GPIO_D2 26 +#define GPIO_D3 27 +#define GPIO_D4 28 +#define GPIO_D5 29 +#define GPIO_D6 30 +#define GPIO_D7 31 + +#define FUNC_TO_GPIO(m) ((m) & 0xfff0) + #endif -- 2.34.1