From dc479f6ebf38c862e75eace7b24c3232249b7ec2 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 20 Jun 2009 07:59:10 +0000 Subject: [PATCH] some comments and cleanup git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73818 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp | 12 ++++++++++-- lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp | 17 ++++------------- 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp index 059bb34bfe0..05f3b6dce2f 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp @@ -818,9 +818,17 @@ void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) { TmpInst.addOperand(MCOp); } - if (TmpInst.getOpcode() == X86::LEA64_32r) { - // Should handle the 'subreg rewriting' for the lea64_32mem operand. + switch (TmpInst.getOpcode()) { + case X86::LEA64_32r: + // Handle the 'subreg rewriting' for the lea64_32mem operand. lower_lea64_32mem(&TmpInst, 1); + break; + case X86::CALL64pcrel32: + case X86::CALLpcrel32: + case X86::TAILJMPd: + // The target operand is pc-relative, not an absolute reference. + // FIXME: this should be an operand property, not an asm format modifier. + ; } // FIXME: Convert TmpInst. diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp index 0311a10a171..fd31aaf9330 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp @@ -348,7 +348,6 @@ void X86ATTAsmPrinter::printOperand(const MCInst *MI, unsigned OpNo, } void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { - const char *Modifier = 0; bool NotRIPRel = false; const MCOperand &BaseReg = MI->getOperand(Op); @@ -368,28 +367,20 @@ void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { } if (IndexReg.getReg() || BaseReg.getReg()) { - unsigned ScaleVal = MI->getOperand(Op+1).getImm(); - unsigned BaseRegOperand = 0, IndexRegOperand = 2; - // There are cases where we can end up with ESP/RSP in the indexreg slot. // If this happens, swap the base/index register to support assemblers that // don't work when the index is *SP. // FIXME: REMOVE THIS. - if (IndexReg.getReg() == X86::ESP || IndexReg.getReg() == X86::RSP) { - assert(ScaleVal == 1 && "Scale not supported for stack pointer!"); - abort(); - //std::swap(BaseReg, IndexReg); - //std::swap(BaseRegOperand, IndexRegOperand); - } + assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP); O << '('; if (BaseReg.getReg()) - printOperand(MI, Op+BaseRegOperand, Modifier); + printOperand(MI, Op); if (IndexReg.getReg()) { O << ','; - printOperand(MI, Op+IndexRegOperand, Modifier); - if (ScaleVal != 1) + printOperand(MI, Op+2); + if (MI->getOperand(Op+1).getImm() != 1) O << ',' << ScaleVal; } O << ')'; -- 2.34.1