From dd254ea7cbf6072f5eeac98fd6d671043b5ce3e6 Mon Sep 17 00:00:00 2001 From: Hao Liu Date: Fri, 22 Nov 2013 09:24:41 +0000 Subject: [PATCH 1/1] Fix a Cygwin build failure caused by enum values starting with '_', which is conflicted with some platform macros. This patch only renames variables, no functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195432 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64RegisterInfo.td | 4 +- .../AArch64/AsmParser/AArch64AsmParser.cpp | 10 +-- .../InstPrinter/AArch64InstPrinter.cpp | 2 +- lib/Target/AArch64/Utils/AArch64BaseInfo.h | 72 +++++++++---------- 4 files changed, 44 insertions(+), 44 deletions(-) diff --git a/lib/Target/AArch64/AArch64RegisterInfo.td b/lib/Target/AArch64/AArch64RegisterInfo.td index 7a7f943b37d..4e2022c0616 100644 --- a/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/lib/Target/AArch64/AArch64RegisterInfo.td @@ -261,12 +261,12 @@ multiclass VectorList_operands"; + "isVectorList"; let ParserMethod = "ParseVectorList"; } def _operand : RegisterOperand"> { + "printVectorList"> { let ParserMatchClass = !cast(PREFIX # LAYOUT # "_asmoperand"); } diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 1e0033c164e..fbbce116ad8 100644 --- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2066,7 +2066,7 @@ AArch64AsmParser::OperandMatchResultTy AArch64AsmParser::ParseVectorList( A64Layout::VectorLayout Layout = A64StringToVectorLayout(LayoutStr); if (Count > 1) { // If count > 1, create vector list using super register. - bool IsVec64 = (Layout < A64Layout::_16B); + bool IsVec64 = (Layout < A64Layout::VL_16B); static unsigned SupRegIDs[3][2] = { { AArch64::QPairRegClassID, AArch64::DPairRegClassID }, { AArch64::QTripleRegClassID, AArch64::DTripleRegClassID }, @@ -2084,10 +2084,10 @@ AArch64AsmParser::OperandMatchResultTy AArch64AsmParser::ParseVectorList( if (Parser.getTok().is(AsmToken::LBrac)) { uint32_t NumLanes = 0; switch(Layout) { - case A64Layout::_B : NumLanes = 16; break; - case A64Layout::_H : NumLanes = 8; break; - case A64Layout::_S : NumLanes = 4; break; - case A64Layout::_D : NumLanes = 2; break; + case A64Layout::VL_B : NumLanes = 16; break; + case A64Layout::VL_H : NumLanes = 8; break; + case A64Layout::VL_S : NumLanes = 4; break; + case A64Layout::VL_D : NumLanes = 2; break; default: SMLoc Loc = getLexer().getLoc(); Error(Loc, "expected comma before next operand"); diff --git a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp index 24205b57b9e..0438de3152e 100644 --- a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp +++ b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp @@ -521,7 +521,7 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum, std::string LayoutStr = A64VectorLayoutToString(Layout); O << "{"; if (Count > 1) { // Print sub registers separately - bool IsVec64 = (Layout < A64Layout::_16B); + bool IsVec64 = (Layout < A64Layout::VL_16B); unsigned SubRegIdx = IsVec64 ? AArch64::dsub_0 : AArch64::qsub_0; for (unsigned I = 0; I < Count; I++) { std::string Name = getRegisterName(MRI.getSubReg(Reg, SubRegIdx++)); diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/lib/Target/AArch64/Utils/AArch64BaseInfo.h index d6ae147182d..ce970b0a8ab 100644 --- a/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -309,40 +309,40 @@ namespace A64SE { namespace A64Layout { enum VectorLayout { Invalid = -1, - _8B, - _4H, - _2S, - _1D, + VL_8B, + VL_4H, + VL_2S, + VL_1D, - _16B, - _8H, - _4S, - _2D, + VL_16B, + VL_8H, + VL_4S, + VL_2D, // Bare layout for the 128-bit vector // (only show ".b", ".h", ".s", ".d" without vector number) - _B, - _H, - _S, - _D + VL_B, + VL_H, + VL_S, + VL_D }; } inline static const char * A64VectorLayoutToString(A64Layout::VectorLayout Layout) { switch (Layout) { - case A64Layout::_8B: return ".8b"; - case A64Layout::_4H: return ".4h"; - case A64Layout::_2S: return ".2s"; - case A64Layout::_1D: return ".1d"; - case A64Layout::_16B: return ".16b"; - case A64Layout::_8H: return ".8h"; - case A64Layout::_4S: return ".4s"; - case A64Layout::_2D: return ".2d"; - case A64Layout::_B: return ".b"; - case A64Layout::_H: return ".h"; - case A64Layout::_S: return ".s"; - case A64Layout::_D: return ".d"; + case A64Layout::VL_8B: return ".8b"; + case A64Layout::VL_4H: return ".4h"; + case A64Layout::VL_2S: return ".2s"; + case A64Layout::VL_1D: return ".1d"; + case A64Layout::VL_16B: return ".16b"; + case A64Layout::VL_8H: return ".8h"; + case A64Layout::VL_4S: return ".4s"; + case A64Layout::VL_2D: return ".2d"; + case A64Layout::VL_B: return ".b"; + case A64Layout::VL_H: return ".h"; + case A64Layout::VL_S: return ".s"; + case A64Layout::VL_D: return ".d"; default: llvm_unreachable("Unknown Vector Layout"); } } @@ -350,18 +350,18 @@ A64VectorLayoutToString(A64Layout::VectorLayout Layout) { inline static A64Layout::VectorLayout A64StringToVectorLayout(StringRef LayoutStr) { return StringSwitch(LayoutStr) - .Case(".8b", A64Layout::_8B) - .Case(".4h", A64Layout::_4H) - .Case(".2s", A64Layout::_2S) - .Case(".1d", A64Layout::_1D) - .Case(".16b", A64Layout::_16B) - .Case(".8h", A64Layout::_8H) - .Case(".4s", A64Layout::_4S) - .Case(".2d", A64Layout::_2D) - .Case(".b", A64Layout::_B) - .Case(".h", A64Layout::_H) - .Case(".s", A64Layout::_S) - .Case(".d", A64Layout::_D) + .Case(".8b", A64Layout::VL_8B) + .Case(".4h", A64Layout::VL_4H) + .Case(".2s", A64Layout::VL_2S) + .Case(".1d", A64Layout::VL_1D) + .Case(".16b", A64Layout::VL_16B) + .Case(".8h", A64Layout::VL_8H) + .Case(".4s", A64Layout::VL_4S) + .Case(".2d", A64Layout::VL_2D) + .Case(".b", A64Layout::VL_B) + .Case(".h", A64Layout::VL_H) + .Case(".s", A64Layout::VL_S) + .Case(".d", A64Layout::VL_D) .Default(A64Layout::Invalid); } -- 2.34.1