From ddcf3ee768d41f16c6f10c38f7faee440d6b9f55 Mon Sep 17 00:00:00 2001 From: Jyotsna Verma Date: Tue, 7 May 2013 17:12:35 +0000 Subject: [PATCH] Reverting r181331. Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/Hexagon.h | 2 - lib/Target/Hexagon/HexagonISelLowering.cpp | 1 + .../Hexagon/HexagonSplitConst32AndConst64.cpp | 176 ------------------ lib/Target/Hexagon/HexagonTargetMachine.cpp | 11 +- .../Hexagon/HexagonTargetObjectFile.cpp | 8 +- lib/Target/Hexagon/HexagonTargetObjectFile.h | 1 - test/CodeGen/Hexagon/split-const32-const64.ll | 26 --- 7 files changed, 3 insertions(+), 222 deletions(-) delete mode 100644 lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp delete mode 100644 test/CodeGen/Hexagon/split-const32-const64.ll diff --git a/lib/Target/Hexagon/Hexagon.h b/lib/Target/Hexagon/Hexagon.h index 8e19c61f400..a9b00a22ac5 100644 --- a/lib/Target/Hexagon/Hexagon.h +++ b/lib/Target/Hexagon/Hexagon.h @@ -37,8 +37,6 @@ namespace llvm { FunctionPass *createHexagonCFGOptimizer(const HexagonTargetMachine &TM); FunctionPass *createHexagonSplitTFRCondSets(const HexagonTargetMachine &TM); - FunctionPass *createHexagonSplitConst32AndConst64( - const HexagonTargetMachine &TM); FunctionPass *createHexagonExpandPredSpillCode( const HexagonTargetMachine &TM); FunctionPass *createHexagonHardwareLoops(); diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index 4e57c45f4a4..0e5b8dcbe88 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -948,6 +948,7 @@ HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { SDValue HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { EVT ValTy = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); ConstantPoolSDNode *CP = cast(Op); SDValue Res; diff --git a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp deleted file mode 100644 index 3bf2f20457e..00000000000 --- a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp +++ /dev/null @@ -1,176 +0,0 @@ -//=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// When the compiler is invoked with no small data, for instance, with the -G0 -// command line option, then all CONST32_* opcodes should be broken down into -// appropriate LO and HI instructions. This splitting is done by this pass. -// The only reason this is not done in the DAG lowering itself is that there -// is no simple way of getting the register allocator to allot the same hard -// register to the result of LO and HI instructions. This pass is always -// scheduled after register allocation. -// -//===----------------------------------------------------------------------===// -#define DEBUG_TYPE "xfer" -#include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/ScheduleDAGInstrs.h" -#include "llvm/CodeGen/LatencyPriorityQueue.h" -#include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/CodeGen/MachineDominators.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineLoopInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/ScheduleHazardRecognizer.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Support/Compiler.h" -#include "llvm/Support/Debug.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "HexagonTargetMachine.h" -#include "HexagonSubtarget.h" -#include "HexagonMachineFunctionInfo.h" -#include -#include - -#include "llvm/Support/CommandLine.h" -#define DEBUG_TYPE "xfer" - - -using namespace llvm; - -namespace { - -class HexagonSplitConst32AndConst64 : public MachineFunctionPass { - const HexagonTargetMachine& QTM; - const HexagonSubtarget &QST; - - public: - static char ID; - HexagonSplitConst32AndConst64(const HexagonTargetMachine& TM) - : MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {} - - const char *getPassName() const { - return "Hexagon Split Const32s and Const64s"; - } - bool runOnMachineFunction(MachineFunction &Fn); -}; - - -char HexagonSplitConst32AndConst64::ID = 0; - - -bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) { - - const TargetInstrInfo *TII = QTM.getInstrInfo(); - - // Loop over all of the basic blocks - for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end(); - MBBb != MBBe; ++MBBb) { - MachineBasicBlock* MBB = MBBb; - // Traverse the basic block - MachineBasicBlock::iterator MII = MBB->begin(); - MachineBasicBlock::iterator MIE = MBB->end (); - while (MII != MIE) { - MachineInstr *MI = MII; - int Opc = MI->getOpcode(); - if (Opc == Hexagon::CONST32_set) { - int DestReg = MI->getOperand(0).getReg(); - MachineOperand &Symbol = MI->getOperand (1); - - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::LO), DestReg).addOperand(Symbol); - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::HI), DestReg).addOperand(Symbol); - // MBB->erase returns the iterator to the next instruction, which is the - // one we want to process next - MII = MBB->erase (MI); - continue; - } - else if (Opc == Hexagon::CONST32_set_jt) { - int DestReg = MI->getOperand(0).getReg(); - MachineOperand &Symbol = MI->getOperand (1); - - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol); - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol); - // MBB->erase returns the iterator to the next instruction, which is the - // one we want to process next - MII = MBB->erase (MI); - continue; - } - else if (Opc == Hexagon::CONST32_Label) { - int DestReg = MI->getOperand(0).getReg(); - MachineOperand &Symbol = MI->getOperand (1); - - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol); - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol); - // MBB->erase returns the iterator to the next instruction, which is the - // one we want to process next - MII = MBB->erase (MI); - continue; - } - else if (Opc == Hexagon::CONST32_Int_Real) { - int DestReg = MI->getOperand(0).getReg(); - int64_t ImmValue = MI->getOperand(1).getImm (); - - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::LOi), DestReg).addImm(ImmValue); - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::HIi), DestReg).addImm(ImmValue); - MII = MBB->erase (MI); - continue; - } - else if (Opc == Hexagon::CONST64_Int_Real) { - int DestReg = MI->getOperand(0).getReg(); - int64_t ImmValue = MI->getOperand(1).getImm (); - unsigned DestLo = - QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_loreg); - unsigned DestHi = - QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_hireg); - - int32_t LowWord = (ImmValue & 0xFFFFFFFF); - int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF; - - // Lower Registers Lower Half - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::LOi), DestLo).addImm(LowWord); - // Lower Registers Higher Half - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::HIi), DestLo).addImm(LowWord); - // Higher Registers Lower Half - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::LOi), DestHi).addImm(HighWord); - // Higher Registers Higher Half. - BuildMI (*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::HIi), DestHi).addImm(HighWord); - MII = MBB->erase (MI); - continue; - } - ++MII; - } - } - - return true; -} - -} - -//===----------------------------------------------------------------------===// -// Public Constructor Functions -//===----------------------------------------------------------------------===// - -FunctionPass * -llvm::createHexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) { - return new HexagonSplitConst32AndConst64(TM); -} diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index 1b023b8e56b..caa1ba49649 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -15,7 +15,6 @@ #include "Hexagon.h" #include "HexagonISelLowering.h" #include "HexagonMachineScheduler.h" -#include "HexagonTargetObjectFile.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Module.h" #include "llvm/PassManager.h" @@ -157,17 +156,9 @@ bool HexagonPassConfig::addPostRegAlloc() { } bool HexagonPassConfig::addPreSched2() { - const HexagonTargetMachine &TM = getHexagonTargetMachine(); - HexagonTargetObjectFile &TLOF = - (HexagonTargetObjectFile&)(getTargetLowering()->getObjFileLowering()); - if (getOptLevel() != CodeGenOpt::None) addPass(&IfConverterID); - if (!TLOF.IsSmallDataEnabled()) { - addPass(createHexagonSplitConst32AndConst64(TM)); - printAndVerify("After hexagon split const32/64 pass"); - } - return true; + return false; } bool HexagonPassConfig::addPreEmitPass() { diff --git a/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/lib/Target/Hexagon/HexagonTargetObjectFile.cpp index 7773cff2d21..993fcfaed43 100644 --- a/lib/Target/Hexagon/HexagonTargetObjectFile.cpp +++ b/lib/Target/Hexagon/HexagonTargetObjectFile.cpp @@ -25,8 +25,7 @@ using namespace llvm; static cl::opt SmallDataThreshold("hexagon-small-data-threshold", - cl::init(8), cl::Hidden, - cl::desc("The maximum size of an object in the sdata section")); + cl::init(8), cl::Hidden); void HexagonTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { @@ -47,11 +46,6 @@ void HexagonTargetObjectFile::Initialize(MCContext &Ctx, static bool IsInSmallSection(uint64_t Size) { return Size > 0 && Size <= (uint64_t)SmallDataThreshold; } - -bool HexagonTargetObjectFile::IsSmallDataEnabled () const { - return SmallDataThreshold > 0; -} - /// IsGlobalInSmallSection - Return true if this global value should be /// placed into small data/bss section. bool HexagonTargetObjectFile::IsGlobalInSmallSection(const GlobalValue *GV, diff --git a/lib/Target/Hexagon/HexagonTargetObjectFile.h b/lib/Target/Hexagon/HexagonTargetObjectFile.h index 41f6792ca8e..693345081ee 100644 --- a/lib/Target/Hexagon/HexagonTargetObjectFile.h +++ b/lib/Target/Hexagon/HexagonTargetObjectFile.h @@ -29,7 +29,6 @@ namespace llvm { bool IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM) const; - bool IsSmallDataEnabled () const; const MCSection* SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler *Mang, diff --git a/test/CodeGen/Hexagon/split-const32-const64.ll b/test/CodeGen/Hexagon/split-const32-const64.ll deleted file mode 100644 index 2815253545c..00000000000 --- a/test/CodeGen/Hexagon/split-const32-const64.ll +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-small-data-threshold=0 < %s | FileCheck %s - -; Check that CONST32/CONST64 instructions are 'not' generated when -; small-data-threshold is set to 0. - -; with immediate value. -@a = external global i32 -@b = external global i32 -@la = external global i64 -@lb = external global i64 - -define void @test1() nounwind { -; CHECK-NOT: CONST32 -entry: - store i32 12345670, i32* @a, align 4 - store i32 12345670, i32* @b, align 4 - ret void -} - -define void @test2() nounwind { -; CHECK-NOT: CONST64 -entry: - store i64 1234567890123, i64* @la, align 8 - store i64 1234567890123, i64* @lb, align 8 - ret void -} -- 2.34.1