From deeacfd957814adb0f812ee2f14440e03ec97acf Mon Sep 17 00:00:00 2001 From: WeiYong Bi Date: Fri, 4 Aug 2017 09:09:12 +0800 Subject: [PATCH] drm/rockchip: dsi: fix Non-SNPS PHY power on sequence Change-Id: If9f131ec6ebc8b194034bf231ca2bcc120440860 Signed-off-by: WeiYong Bi --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 9e2585372432..ffe4f0a52323 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -1112,6 +1112,13 @@ static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi) return; } + if (dsi->dphy.phy) { + rockchip_dsi_set_hs_clk(dsi); + phy_power_on(dsi->dphy.phy); + } else { + dw_mipi_dsi_get_lane_bps(dsi); + } + pm_runtime_get_sync(dsi->dev); if (dsi->rst) { @@ -1122,13 +1129,6 @@ static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi) udelay(10); } - if (dsi->dphy.phy) { - rockchip_dsi_set_hs_clk(dsi); - phy_power_on(dsi->dphy.phy); - } else { - dw_mipi_dsi_get_lane_bps(dsi); - } - dev_info(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n", dsi->lane_mbps, dsi->lanes); } -- 2.34.1