From e005a304156b554ac6bed9e4a9130ba675b35653 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Thu, 17 Jul 2014 22:23:54 +0800 Subject: [PATCH] ARM: rockchip: rk3036 add cpu axi bus support --- arch/arm/boot/dts/rk3036.dtsi | 45 ++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/cpu_axi.h | 3 ++- 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 7c5f838cbcf2..837e54efc320 100755 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -50,6 +50,51 @@ ; }; + cpu_axi_bus: cpu_axi_bus { + compatible = "rockchip,cpu_axi_bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qos { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + core { + reg = <0x1012a000 0x20>; + rockchip,priority = <3 2>; + }; + peri { + reg = <0x1012c000 0x20>; + }; + gpu { + reg = <0x1012d000 0x20>; + }; + vpu { + reg = <0x1012e000 0x20>; + }; + hevc { + reg = <0x1012e080 0x20>; + }; + vio { + reg = <0x1012f000 0x20>; + rockchip,priority = <3 3>; + }; + }; + + msch { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + msch@10128000 { + reg = <0x10128000 0x40>; + rockchip,read-latency = <0x80>; + }; + }; + }; + sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x2000>; diff --git a/arch/arm/mach-rockchip/cpu_axi.h b/arch/arm/mach-rockchip/cpu_axi.h index 4c346dec79f2..53a94f108285 100644 --- a/arch/arm/mach-rockchip/cpu_axi.h +++ b/arch/arm/mach-rockchip/cpu_axi.h @@ -12,7 +12,8 @@ #define CPU_AXI_QOS_MODE_LIMITER 2 #define CPU_AXI_QOS_MODE_REGULATOR 3 -#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 2) | ((l) & 3)) +#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \ + ((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3)) #define CPU_AXI_SET_QOS_PRIORITY(h, l, base) \ writel_relaxed(CPU_AXI_QOS_PRIORITY_LEVEL(h, l), base + CPU_AXI_QOS_PRIORITY) -- 2.34.1