From e05910e6770e95a1aee6d3ac4c5ced059a6e3c7f Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 9 Jul 2015 16:30:27 +0000 Subject: [PATCH] AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal() No test case for this. I ran into it while working on some improvements to SIShrinkInstructions.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241816 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIInstrInfo.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index eb96bd0227b..288ab7523e3 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1625,7 +1625,10 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx, if (MO->isReg()) { assert(DefinedRC); - const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg()); + const TargetRegisterClass *RC = + TargetRegisterInfo::isVirtualRegister(MO->getReg()) ? + MRI.getRegClass(MO->getReg()) : + RI.getPhysRegClass(MO->getReg()); // In order to be legal, the common sub-class must be equal to the // class of the current operand. For example: -- 2.34.1