From e1820a6a4e5cfd1a41bd40ce6c21635d04289fec Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Mon, 10 Mar 2014 15:01:57 +0000 Subject: [PATCH] [mips][fp64] Add an implicit def to MFHC1 claiming that it reads the lower 32-bits of 64-bit FPR Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MFHC1 to be scheduled on the wrong side of most 32-bit FPU ops. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. MFHC1 is one of two affected instructions. These instructions are the only FPU instructions that don't read or write the lower 32-bits. We therefore pretend that it reads the bottom 32-bits to artificially create a dependency and prevent the scheduler changing the behaviour of the code. The other instruction is MTHC1 which will be fixed once I've have found a failing test case for it. The testcase is test-suite/SingleSource/UnitTests/Vector/simple.c when given TARGET_CFLAGS="-mips32r2 -mfp64 -mmsa". Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2966 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203464 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsSEInstrInfo.cpp | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index 96aaf26d007..a7ade1f47b2 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -506,9 +506,21 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); - if (SubIdx == Mips::sub_hi && FP64) - BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg); - else + if (SubIdx == Mips::sub_hi && FP64) { + // FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to + // temporarily work around a widespread bug in the -mfp64 support. + // The problem is that none of the 32-bit fpu ops mention the fact + // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that + // requires a major overhaul of the FPU implementation which can't + // be done right now due to time constraints. + // MFHC1 is the only instruction that is affected since it is the + // only instruction that doesn't read the lower 32-bits. We therefore + // pretend that it reads the bottom 32-bits to artificially create a + // dependency and prevent the scheduler changing the behaviour of the + // code. + BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg( + SrcReg, RegState::Implicit); + } else BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); } -- 2.34.1