From e21df2959179efc289cee9c17a67e5bc9e3c157a Mon Sep 17 00:00:00 2001 From: WeiYong Bi Date: Mon, 17 Jul 2017 10:58:32 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3368: export MIPI DPHY PLL clock Change-Id: I15ef0a01cde0459d1993110f5653f6bf10f99a64 Signed-off-by: WeiYong Bi --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 409722c6e278..167531b4cc6d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -1426,8 +1426,8 @@ compatible = "rockchip,rk3368-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x4000>; interrupts = ; - clocks = <&cru PCLK_MIPI_DSI0>; - clock-names = "pclk"; + clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>; + clock-names = "pclk", "hs_clk"; resets = <&cru SRST_MIPIDSI0>; reset-names = "apb"; phys = <&mipi_dphy>; @@ -1450,11 +1450,13 @@ mipi_dphy: mipi-dphy@ff968000 { compatible = "rockchip,rk3368-mipi-dphy"; reg = <0x0 0xff968000 0x0 0x4000>; - #phy-cells = <0>; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>; clock-names = "ref", "pclk"; + clock-output-names = "mipi_dphy_pll"; + #clock-cells = <0>; resets = <&cru SRST_MIPIDPHYTX>; reset-names = "apb"; + #phy-cells = <0>; status = "disabled"; }; -- 2.34.1