From e2b32bb20ee76f24708b3c9e19b6fbc651c25637 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Fri, 22 Jun 2012 02:50:33 +0000 Subject: [PATCH] ARM scheduling fix: don't guess at implicit operand latency. This is a minor drive-by fix with no robust way to unit test. As an example see neon-div.ll: SU(16): %Q8 = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8 val SU(1): Latency=2 Reg=%Q8 ...should be latency=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158960 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseInstrInfo.cpp | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index cceb05e4615..e30f6d200ca 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2746,11 +2746,12 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, unsigned NewUseIdx; const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, Reg, NewUseIdx, UseAdj); - if (NewUseMI) { - UseMI = NewUseMI; - UseIdx = NewUseIdx; - UseMCID = &UseMI->getDesc(); - } + if (!NewUseMI) + return -1; + + UseMI = NewUseMI; + UseIdx = NewUseIdx; + UseMCID = &UseMI->getDesc(); } if (Reg == ARM::CPSR) { @@ -2778,6 +2779,9 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, return Latency; } + if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) + return -1; + unsigned DefAlign = DefMI->hasOneMemOperand() ? (*DefMI->memoperands_begin())->getAlignment() : 0; unsigned UseAlign = UseMI->hasOneMemOperand() -- 2.34.1