From e2f0909ced4d740a0c1402439df13847e2789254 Mon Sep 17 00:00:00 2001 From: lhh Date: Wed, 20 Oct 2010 17:31:21 +0800 Subject: [PATCH] add rk29 phys --- arch/arm/mach-rk29/include/mach/irqs.h | 76 +++++++++++- arch/arm/mach-rk29/include/mach/rk29_iomap.h | 121 +++++++++++++++++-- 2 files changed, 184 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-rk29/include/mach/irqs.h b/arch/arm/mach-rk29/include/mach/irqs.h index 72fab364ca2d..070b7f3f7474 100644 --- a/arch/arm/mach-rk29/include/mach/irqs.h +++ b/arch/arm/mach-rk29/include/mach/irqs.h @@ -17,10 +17,76 @@ #ifndef __ARCH_ARM_MACH_RK29_IRQS_H #define __ARCH_ARM_MACH_RK29_IRQS_H -#define NR_IRQS 64 -#define IRQ_NR_TIMER0 15 -#define IRQ_NR_TIMER1 16 -#define IRQ_NR_TIMER2 17 -#define IRQ_NR_TIMER3 18 +#define NR_IRQS 68 +/*irq number*/ +#define IRQ_NR_DMAC00 0 +#define IRQ_NR_DMAC01 1 +#define IRQ_NR_DMAC000 2 +#define IRQ_NR_DMAC010 3 +#define IRQ_NR_DMAC20 4 +#define IRQ_NR_DMAC21 5 +#define IRQ_NR_DMAC22 6 +#define IRQ_NR_DMAC23 7 +#define IRQ_NR_DMAC24 8 +#define IRQ_NR_GPU 9 +#define IRQ_NR_VEPU 10 +#define IRQ_NR_VDPU 11 +#define IRQ_NR_VIP 12 +#define IRQ_NR_LCDC 13 +#define IRQ_NR_IPP 14 +#define IRQ_NR_EBC 15 +#define IRQ_NR_USBOTG0 16 +#define IRQ_NR_USBOTG1 17 +#define IRQ_NR_USBHOST 18 +#define IRQ_NR_MAC 19 +#define IRQ_NR_HIF0 20 +#define IRQ_NR_HIF1 21 +#define IRQ_NR_HSADC_TS1 22 +#define IRQ_NR_SDMMC 23 +#define IRQ_NR_SDIO 24 +#define IRQ_NR_EMMC 25 +#define IRQ_NR_SARADC 26 +#define IRQ_NR_NANDC 27 +#define IRQ_NR_NANDCRDY 28 +#define IRQ_NR_SMC 29 +#define IRQ_NR_PID_FILTER 30 +#define IRQ_NR_I2SPCM8 31 +#define IRQ_NR_I2SPCM2 32 +#define IRQ_NR_SPDIF 33 +#define IRQ_NR_UART0 34 +#define IRQ_NR_UART1 35 +#define IRQ_NR_UART2 36 +#define IRQ_NR_UART3 37 +#define IRQ_NR_SPI0 38 +#define IRQ_NR_SPI1 39 +#define IRQ_NR_I2C0 40 +#define IRQ_NR_I2C1 41 +#define IRQ_NR_I2C2 42 +#define IRQ_NR_I2C3 43 +#define IRQ_NR_TIMER0 44 +#define IRQ_NR_TIMER1 45 +#define IRQ_NR_TIMER2 46 +#define IRQ_NR_TIMER3 47 +#define IRQ_NR_PWM0 48 +#define IRQ_NR_PWM1 49 +#define IRQ_NR_PWM2 50 +#define IRQ_NR_PWM3 51 +#define IRQ_NR_WDT 52 +#define IRQ_NR_RTC 53 +#define IRQ_NR_PMU 54 +#define IRQ_NR_GPIO0 55 +#define IRQ_NR_GPIO1 56 +#define IRQ_NR_GPIO2 57 +#define IRQ_NR_GPIO3 58 +#define IRQ_NR_GPIO4 59 +#define IRQ_NR_GPIO5 60 +#define IRQ_NR_GPIO6 61 +#define IRQ_NR_USB_AHB_ARB 62 +#define IRQ_NR_PERI_AHB_ARB 63 +#define IRQ_NR_A8IRQ0 64 +#define IRQ_NR_A8IRQ1 65 +#define IRQ_NR_A8IRQ2 66 +#define IRQ_NR_A8IRQ3 67 + #endif diff --git a/arch/arm/mach-rk29/include/mach/rk29_iomap.h b/arch/arm/mach-rk29/include/mach/rk29_iomap.h index 9c18b2df4912..274e5efa2223 100644 --- a/arch/arm/mach-rk29/include/mach/rk29_iomap.h +++ b/arch/arm/mach-rk29/include/mach/rk29_iomap.h @@ -24,48 +24,153 @@ *ºÍÒÔ0x10000000Ϊ»ùµØÖ··ÖÁíÓ³ÉäΪ£º0xf5000000, *0xf4000000 */ + + #define RK29_ADDR_BASE1 0xF5000000 #define RK29_ADDR_BASE0 0xF4000000 #define RK29_SDRAM_PHYS 0x60000000 -#define RK29_AXI0_PHYS 0x1012C000 #define RK29_AXI1_PHYS 0x10000000 +#define RK29_AXI0_PHYS 0x1012C000 #define RK29_PERI_PHYS 0x10140000 +//CPU system AXI 1 #define RK29_BOOTROM_PHYS 0x10100000 #define RK29_BOOTROM_SIZE SZ_16K - +#define RK29_VCODEC_PHYS 0x10104000 +#define RK29_VCODEC_SIZE SZ_16K +#define RK29_VIP_PHYS 0x10108000 +#define RK29_VIP_SIZE SZ_16K +#define RK29_LCDC_PHYS 0x1010C000 +#define RK29_LCDC_SIZE SZ_16K +#define RK29_IPP_PHYS 0x10110000 +#define RK29_IPP_SIZE SZ_16K +#define RK29_EBC_PHYS 0x10114000 +#define RK29_EBC_SIZE SZ_16K +#define RK29_I2S_8CH_PHYS 0x10118000 +#define RK29_I2S_8CH_SIZE SZ_16K +#define RK29_I2S_2CH_PHYS 0x1011C000 +#define RK29_I2S_2CH_SIZE SZ_8K +#define RK29_SPDIF_PHYS 0x1011E000 +#define RK29_SPDIF_SIZE SZ_8K +#define RK29_GPU_PHYS 0x10120000 +#define RK29_GPU_PHYS_SIZE SZ_16K #define RK29_DDRC_PHYS 0x10124000 #define RK29_DDRC_BASE (RK29_ADDR_BASE0+0x124000) #define RK29_DDRC_SIZE SZ_16K +//CPU system AXI 0 #define RK29_GICCPU_PHYS 0x1012C000 #define RK29_GICCPU_BASE (RK29_ADDR_BASE0+0x12C000) #define RK29_GICCPU_SIZE SZ_8K - #define RK29_GICPERI_PHYS 0x1012E000 #define RK29_GICPERI_BASE (RK29_ADDR_BASE0+0x12E000) #define RK29_GICPERI_SIZE SZ_8K +#define RK29_CPU_AXI_BUS0_PHYS 0x15000000 +//peri system #define RK29_USBHOST_PHYS 0x10140000 #define RK29_USBHOST_SIZE SZ_256K - #define RK29_USBOTG0_PHYS 0x10180000 #define RK29_USBOTG0_SIZE SZ_256K - #define RK29_USBOTG1_PHYS 0x101c0000 #define RK29_USBOTG1_SIZE SZ_256K - -#define RK29_NANDC_PHYS 0x1012E000 +#define RK29_MAC_PHYS 0x10204000 +#define RK29_MAC_SIZE SZ_16K +#define RK29_HOSTIF_PHYS 0x1020C000 +#define RK29_HOSTIF_SIZE SZ_16K +#define RK29_HSADC_PHYS 0x10210000 +#define RK29_HSADC_SIZE SZ_16K +#define RK29_SDMMC0_PHYS 0x10214000 +#define RK29_SDMMC0_SIZE SZ_16K +#define RK29_SDMMC1_PHYS 0x10218000 +#define RK29_SDMMC1_SIZE SZ_16K +#define RK29_EMMC_PHYS 0x1021C000 +#define RK29_EMMC_SIZE SZ_16K +#define RK29_PIDF_PHYS 0x10220000 +#define RK29_EMMC_SIZE SZ_16K +#define RK29_ARBITER0_PHYS 0x10224000 +#define RK29_ARBITER0_SIZE SZ_16K +#define RK29_ARBITER1_PHYS 0x10228000 +#define RK29_ARBITER1_SIZE SZ_16K +#define RK29_PERI_AXI_BUS0_PHYS 0x10300000 +#define RK29_NANDC_PHYS 0x10500000 #define RK29_NANDC_BASE (RK29_ADDR_BASE0+0x500000) #define RK29_NANDC_SIZE SZ_16K +//CPU AXI 1 APB +#define RK29_CRU_PHYS 0x20000000 +#define RK29_CRU_SIZE SZ_16K +#define RK29_PMU_PHYS 0x20004000 +#define RK29_PMU_SIZE SZ_16K +#define RK29_GRF_PHYS 0x20008000 +#define RK29_GRF_SIZE SZ_16K +#define RK29_RTC_PHYS 0x2000C000 +#define RK29_RTC_SIZE SZ_16K +#define RK29_EFUSE_PHYS 0x20010000 +#define RK29_EFUSE_SIZE SZ_16K +#define RK29_TZPC_PHYS 0x20014000 +#define RK29_TZPC_SIZE SZ_16K +#define RK29_SDMAC0_PHYS 0x20018000 +#define RK29_SDMAC0_SIZE SZ_16K +#define RK29_DMAC0_PHYS 0x2001C000 +#define RK29_DMAC0_SIZE SZ_16K +#define RK29_DEBUG_PHYS 0x20024000 +#define RK29_DEBUG_SIZE SZ_16K +#define RK29_I2C0_PHYS 0x2002C000 +#define RK29_I2C0_SIZE SZ_16K +#define RK29_UART0_PHYS 0x20030000 +#define RK29_UART0_SIZE SZ_16K +#define RK29_GPIO0_PHYS 0x20034000 +#define RK29_GPIO0_SIZE SZ_16K #define RK29_TIMER0_BASE (RK29_ADDR_BASE1+0x38000) #define RK29_TIMER0_PHYS 0x20038000 #define RK29_TIMER0_SIZE SZ_8K +#define RK29_TIMER1_PHYS 0x2003A000 +#define RK29_TIMER0_SIZE SZ_8K +#define RK29_GPIO4_PHYS 0x2003C000 +#define RK29_GPIO4_SIZE SZ_8K +#define RK29_GPIO6_PHYS 0x2003E000 +#define RK29_GPIO6_SIZE SZ_8K +//peri system APB +#define RK29_TIMER2_PHYS 0x20044000 +#define RK29_TIMER2_SIZE SZ_16K +#define RK29_TIMER3_PHYS 0x20048000 +#define RK29_TIMER3_SIZE SZ_16K +#define RK29_WDT_PHYS 0x2004C000 +#define RK29_WDT_SIZE SZ_16K +#define RK29_PWM_PHYS 0x20050000 +#define RK29_PWM_SIZE SZ_16K +#define RK29_I2C1_PHYS 0x20054000 +#define RK29_I2C1_SIZE SZ_16K +#define RK29_I2C2_PHYS 0x20058000 +#define RK29_I2C2_SIZE SZ_16K +#define RK29_I2C3_PHYS 0x2005C000 +#define RK29_I2C3_SIZE SZ_16K #define RK29_UART1_PHYS 0x20060000 #define RK29_UART1_BASE (RK29_ADDR_BASE1+0x60000) #define RK29_UART1_SIZE SZ_16K - +#define RK29_UART2_PHYS 0x20064000 +#define RK29_UART2_SIZE SZ_16K +#define RK29_UART3_PHYS 0x20068000 +#define RK29_TIMER2_SIZE SZ_16K +#define RK29_ADC_PHYS 0x2006C000 +#define RK29_ADC_SIZE SZ_16K +#define RK29_SPI0_PHYS 0x20070000 +#define RK29_SPI0_SIZE SZ_16K +#define RK29_SPI1_PHYS 0x20074000 +#define RK29_SPI1_SIZE SZ_16K +#define RK29_DMA2_PHYS 0x20078000 +#define RK29_DMA2_SIZE SZ_16K +#define RK29_SMC_PHYS 0x2007C000 +#define RK29_SMC_SIZE SZ_16K +#define RK29_GPIO1_PHYS 0x20080000 +#define RK29_GPIO1_SIZE SZ_16K +#define RK29_GPIO2_PHYS 0x20084000 +#define RK29_GPIO2_SIZE SZ_16K +#define RK29_GPIO3_PHYS 0x20088000 +#define RK29_GPIO3_SIZE SZ_16K +#define RK29_GPIO5_PHYS 0x2008C000 +#define RK29_GPIO5_SIZE SZ_16K #endif -- 2.34.1