From e3e8445fd7844bec1efe7f7b879eecfc42e50266 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Mon, 10 Mar 2014 18:25:27 +0800 Subject: [PATCH] ARM: rockchip: rk3288.dtsi indent only --- arch/arm/boot/dts/rk3288.dtsi | 258 +++++++++++++++++----------------- 1 file changed, 128 insertions(+), 130 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 01982ee26e86..4ff977f7d7e9 100755 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -96,8 +96,6 @@ status = "disabled"; }; - - i2c0: i2c@ff650000 { compatible = "rockchip,rk30-i2c"; reg = <0xff650000 0x1000>; @@ -173,30 +171,29 @@ status = "disabled"; }; - - i2c5: i2c@ff170000 { - compatible = "rockchip,rk30-i2c"; - reg = <0xff170000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - //pinctrl-names = "default", "gpio"; - //pinctrl-0 = <&i2c5_sda &i2c5_scl>; - //pinctrl-1 = <&i2c5_gpio>; - //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>; - //clocks = <&clk_gates8 8>; - rockchip,check-idle = <1>; - status = "disabled"; - }; + i2c5: i2c@ff170000 { + compatible = "rockchip,rk30-i2c"; + reg = <0xff170000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default", "gpio"; + //pinctrl-0 = <&i2c5_sda &i2c5_scl>; + //pinctrl-1 = <&i2c5_gpio>; + //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>; + //clocks = <&clk_gates8 8>; + rockchip,check-idle = <1>; + status = "disabled"; + }; edp: edp@ff970000 { - compatible = "rockchip,rk32-edp"; - reg = <0xff970000 0x4000>; - interrupts = ; - status = "disabled"; + compatible = "rockchip,rk32-edp"; + reg = <0xff970000 0x4000>; + interrupts = ; + status = "disabled"; }; - hdmi:hdmi@ff980000 { + hdmi: hdmi@ff980000 { compatible = "rockchip,rk3288-hdmi"; reg = <0xff980000 0x20000>; interrupts = ; @@ -205,13 +202,13 @@ pinctrl-0 = <&i2c5_sda &i2c5_scl>; pinctrl-1 = <&i2c5_gpio>; status = "disabled"; - }; + }; fb: fb{ compatible = "rockchip,rk-fb"; rockchip,disp-mode = ; }; - lcdc0:lcdc@ff940000 { + lcdc0: lcdc@ff940000 { compatible = "rockchip,rk3288-lcdc"; rockchip,prop = ; rochchip,pwr18 = <0>; @@ -223,7 +220,7 @@ status = "disabled"; }; - lcdc1:lcdc@ff930000 { + lcdc1: lcdc@ff930000 { compatible = "rockchip,rk3288-lcdc"; rockchip,prop = ; rockchip,pwr18 = <0>; @@ -233,26 +230,26 @@ pinctrl-0 = <&lcdc0_lcdc>; pinctrl-1 = <&lcdc0_gpio>; status = "disabled"; - }; + }; + + adc: adc@ff100000 { + compatible = "rockchip,saradc"; + reg = <0xff100000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + io-channel-ranges; + rockchip,adc-vref = <1800>; + clock-frequency = <1000000>; + clock-names = "saradc", "pclk_saradc"; + status = "disabled"; + }; - adc: adc@ff100000 { - compatible = "rockchip,saradc"; - reg = <0xff100000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - io-channel-ranges; - rockchip,adc-vref = <1800>; - clock-frequency = <1000000>; - clock-names = "saradc", "pclk_saradc"; - status = "disabled"; - }; - rga@ff920000 { compatible = "rockchip,rga"; reg = <0xff920000 0x1000>; interrupts = ; clock-names = "hclk_rga", "aclk_rga"; - }; + }; i2s: rockchip-i2s@0xff890000 { compatible = "rockchip-i2s"; @@ -283,7 +280,8 @@ // pinctrl-names = "default"; // pinctrl-0 = <&spdif_tx>; }; - ion: ion{ + + ion: ion { compatible = "rockchip,ion"; #address-cells = <1>; #size-cells = <0>; @@ -294,115 +292,115 @@ reg = <3>; }; }; - + mmc: mshc@ff0c0000 { - compatible = "rockchip,rk_mmc"; - reg = <0xff0c0000 0x4000>; - interrupts = ; /*irq=64*/ - #address-cells = <1>; - #size-cells = <0>; - //pinctrl-names = "default","suspend"; - //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_cd &sdmmc0_wp &sdmmc0_pwr &sdmmc0_bus1 &sdmmc0_bus4>; - //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio? - //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>; - //clock-names = "hclk_mmc","mmc"; - clock-frequency = <50000000>; - clock-freq-min-max = <400000 50000000>; - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/ - fifo-depth = <0x100>; - emmc-compatible = <0>; - status = "okay"; + compatible = "rockchip,rk_mmc"; + reg = <0xff0c0000 0x4000>; + interrupts = ; /*irq=64*/ + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default","suspend"; + //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_cd &sdmmc0_wp &sdmmc0_pwr &sdmmc0_bus1 &sdmmc0_bus4>; + //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio? + //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>; + //clock-names = "hclk_mmc","mmc"; + clock-frequency = <50000000>; + clock-freq-min-max = <400000 50000000>; + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/ + fifo-depth = <0x100>; + emmc-compatible = <0>; + status = "okay"; }; - + sdio0: mshc@ff0d0000 { compatible = "rockchip,rk_mmc"; - reg = <0xff0d0000 0x4000>; - interrupts = ; /*irq=65*/ - #address-cells = <1>; - #size-cells = <0>; - //pinctrl-names = "default"; - //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>; - //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>; - //clock-names = "hclk_sdio0","sdio0"; - clock-frequency = <50000000>; - clock-freq-min-max = <400000 50000000>; - num-slots = <1>; - supports-highspeed; - fifo-depth = <0x100>; - emmc-compatible = <0>; - status = "disabled"; + reg = <0xff0d0000 0x4000>; + interrupts = ; /*irq=65*/ + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>; + //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>; + //clock-names = "hclk_sdio0","sdio0"; + clock-frequency = <50000000>; + clock-freq-min-max = <400000 50000000>; + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x100>; + emmc-compatible = <0>; + status = "disabled"; }; sdio1: mshc@ff0e0000 { compatible = "rockchip,rk_mmc"; - reg = <0xff0e0000 0x4000>; - interrupts = ; /*irq=66*/ - #address-cells = <1>; - #size-cells = <0>; - //pinctrl-names = "default"; - //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>; - //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>; - //clock-names = "hclk_sdio1","sdio1"; - clock-frequency = <50000000>; - clock-freq-min-max = <400000 50000000>; - num-slots = <1>; - supports-highspeed; - fifo-depth = <0x100>; - emmc-compatible = <0>; - status = "disabled"; + reg = <0xff0e0000 0x4000>; + interrupts = ; /*irq=66*/ + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>; + //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>; + //clock-names = "hclk_sdio1","sdio1"; + clock-frequency = <50000000>; + clock-freq-min-max = <400000 50000000>; + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x100>; + emmc-compatible = <0>; + status = "disabled"; }; emmc: mshc@ff0f0000 { compatible = "rockchip,rk_mmc"; - reg = <0xff0f0000 0x4000>; - interrupts = ; /*irq=67*/ - #address-cells = <1>; - #size-cells = <0>; - //pinctrl-names = "default"; - //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>; - //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>; - //clock-names = "hclk_sdio1","sdio1"; - clock-frequency = <50000000>; - clock-freq-min-max = <400000 50000000>; - num-slots = <1>; - supports-highspeed; - fifo-depth = <0x100>; - emmc-compatible = <1>; - status = "disabled"; + reg = <0xff0f0000 0x4000>; + interrupts = ; /*irq=67*/ + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>; + //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>; + //clock-names = "hclk_sdio1","sdio1"; + clock-frequency = <50000000>; + clock-freq-min-max = <400000 50000000>; + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x100>; + emmc-compatible = <1>; + status = "disabled"; }; - vpu:vpu_service@ff9a0000 { + vpu: vpu_service@ff9a0000 { compatible = "vpu_service"; reg = <0xff9a0000 0x800>; - interrupts = , ; - interrupt-names = "irq_enc", "irq_dec"; - /*clocks = <&clk_gates3 9>, <&clk_gates3 10>; - clock-names = "aclk_vcodec", "hclk_vcodec"; */ - name = "vpu_service"; - status = "disabled"; + interrupts = , ; + interrupt-names = "irq_enc", "irq_dec"; + /*clocks = <&clk_gates3 9>, <&clk_gates3 10>; + clock-names = "aclk_vcodec", "hclk_vcodec"; */ + name = "vpu_service"; + status = "disabled"; }; - hevc:hevc_service@ff9c0000 { - compatible = "rockchip,hevc_service"; - reg = <0xff9c0000 0x800>; - interrupts = ; - interrupt-names = "irq_dec"; - /*clocks = <&clk_gates3 9>, <&clk_gates3 10>; - clock-names = "aclk_vcodec", "hclk_vcodec";*/ - name = "hevc_service"; - status = "disabled"; - }; + hevc: hevc_service@ff9c0000 { + compatible = "rockchip,hevc_service"; + reg = <0xff9c0000 0x800>; + interrupts = ; + interrupt-names = "irq_dec"; + /*clocks = <&clk_gates3 9>, <&clk_gates3 10>; + clock-names = "aclk_vcodec", "hclk_vcodec";*/ + name = "hevc_service"; + status = "disabled"; + }; - iep:iep@ff900000 { - compatible = "rockchip,iep"; - reg = <0xff900000 0x800>; - interrupts = ; - /*clocks = <&clk_gate3 9>, <&clk_gate3 10>; - clock_names = "aclk_iep", "hclk_iep";*/ + iep: iep@ff900000 { + compatible = "rockchip,iep"; + reg = <0xff900000 0x800>; + interrupts = ; + /*clocks = <&clk_gate3 9>, <&clk_gate3 10>; + clock_names = "aclk_iep", "hclk_iep";*/ status = "disabled"; }; }; -- 2.34.1