From e52240c3705f3133eb8c4ebb4220054c68de2651 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 13 Jul 2011 19:12:32 +0000 Subject: [PATCH] Add tests for ARM parsing of 'BIC' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/ARM/basic-arm-instructions.s | 58 ++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 350287bc683..947f40b41cf 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -252,3 +252,61 @@ _func: @------------------------------------------------------------------------------ @ FIXME: BFI @------------------------------------------------------------------------------ + +@------------------------------------------------------------------------------ +@ FIXME: BIC +@------------------------------------------------------------------------------ + bic r10, r1, #0xf + bic r10, r1, r6 + bic r10, r1, r6, lsl #10 + bic r10, r1, r6, lsr #10 + bic r10, r1, r6, lsr #10 + bic r10, r1, r6, asr #10 + bic r10, r1, r6, ror #10 + bic r6, r7, r8, lsl r2 + bic r6, r7, r8, lsr r2 + bic r6, r7, r8, asr r2 + bic r6, r7, r8, ror r2 + bic r10, r1, r6, rrx + + @ destination register is optional + bic r1, #0xf + bic r10, r1 + bic r10, r1, lsl #10 + bic r10, r1, lsr #10 + bic r10, r1, lsr #10 + bic r10, r1, asr #10 + bic r10, r1, ror #10 + bic r6, r7, lsl r2 + bic r6, r7, lsr r2 + bic r6, r7, asr r2 + bic r6, r7, ror r2 + bic r10, r1, rrx + +@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3] +@ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, asr #10 @ encoding: [0x46,0xa5,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, ror #10 @ encoding: [0x66,0xa5,0xc1,0xe1] +@ CHECK: bic r6, r7, r8, lsl r2 @ encoding: [0x18,0x62,0xc7,0xe1] +@ CHECK: bic r6, r7, r8, lsr r2 @ encoding: [0x38,0x62,0xc7,0xe1] +@ CHECK: bic r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0xc7,0xe1] +@ CHECK: bic r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0xc7,0xe1] +@ CHECK: bic r10, r1, r6, rrx @ encoding: [0x66,0xa0,0xc1,0xe1] + + +@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3] +@ CHECK: bic r10, r10, r1 @ encoding: [0x01,0xa0,0xca,0xe1] +@ CHECK: bic r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0xca,0xe1] +@ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1] +@ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1] +@ CHECK: bic r10, r10, r1, asr #10 @ encoding: [0x41,0xa5,0xca,0xe1] +@ CHECK: bic r10, r10, r1, ror #10 @ encoding: [0x61,0xa5,0xca,0xe1] +@ CHECK: bic r6, r6, r7, lsl r2 @ encoding: [0x17,0x62,0xc6,0xe1] +@ CHECK: bic r6, r6, r7, lsr r2 @ encoding: [0x37,0x62,0xc6,0xe1] +@ CHECK: bic r6, r6, r7, asr r2 @ encoding: [0x57,0x62,0xc6,0xe1] +@ CHECK: bic r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0xc6,0xe1] +@ CHECK: bic r10, r10, r1, rrx @ encoding: [0x61,0xa0,0xca,0xe1] + -- 2.34.1