From e524362fcdb544d3fe544ea9028d2edfdc343cae Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E8=AE=B8=E7=9B=9B=E9=A3=9E?= Date: Fri, 4 Jul 2014 10:38:48 +0800 Subject: [PATCH] 3036: fix pwm dts tree --- arch/arm/boot/dts/rk3036.dtsi | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 4b0c46ed4ba4..04023ec9a76b 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -247,7 +247,7 @@ //pinctrl-0 = <&spdif_tx>; }; - pwm: pwm@20050000 { + pwm0: pwm@20050000 { compatible = "rockchip,rk-pwm"; reg = <0x20050000 0x10>; #pwm-cells = <2>; @@ -258,6 +258,39 @@ status = "disabled"; }; + pwm1: pwm@20050010 { + compatible = "rockchip,rk-pwm"; + reg = <0x20050010 0x10>; + #pwm-cells = <2>; + //pinctrl-names = "default"; + //pinctrl-0 = <&pwm_pin>; + clocks = <&clk_gates7 10>; + clock-names = "pclk_pwm"; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + //pinctrl-names = "default"; + //pinctrl-0 = <&pwm_pin>; + clocks = <&clk_gates7 10>; + clock-names = "pclk_pwm"; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + //pinctrl-names = "default"; + //pinctrl-0 = <&pwm_pin>; + clocks = <&clk_gates7 10>; + clock-names = "pclk_pwm"; + status = "disabled"; + }; + emmc: rksdmmc@1021c000 { compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc"; reg = <0x1021c000 0x4000>; -- 2.34.1