From e623668278dc9e27a1892562bcf4cab7933ca2f3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E8=AE=B8=E7=9B=9B=E9=A3=9E?= Date: Wed, 30 Apr 2014 10:49:48 +0800 Subject: [PATCH] pwm: add rockchip-pwm.txt --- .../devicetree/bindings/pwm/rockchip-pwm.txt | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/rockchip-pwm.txt diff --git a/Documentation/devicetree/bindings/pwm/rockchip-pwm.txt b/Documentation/devicetree/bindings/pwm/rockchip-pwm.txt new file mode 100644 index 000000000000..74a0001e64bc --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/rockchip-pwm.txt @@ -0,0 +1,31 @@ +Rockchip PWM controller + +Required properties: +- compatible: should be "rockchip,-pwm" +- reg: physical base address and length of the controller's registers +- #pwm-cells: should be 2. The first cell specifies the per-chip index + of the PWM to use and the second cell is the period in nanoseconds. +- pinctrl-names: must contain a "default" entry. +- pinctrl-0: the pincontrol settings to configurethe. +- clocks: phandle to the PWM source clock +- clock-names: list of clock names sorted in the same order as the clocks. +- status: for device state control (enabled/disabled). + +Example: + +pwm1: pwm@53fb4000 { + #pwm-cells = <2>; + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb4000 0x4000>; + interrupts = <61>; +}; +pwm0: pwm@ff680000 { + compatible = "rockchip,rk-pwm"; + reg = <0xff680000 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&clk_gates11 11>; + clock-names = "pclk_pwm"; + status = "disabled"; +}; -- 2.34.1