From e67304fb7880bd55d194d68b827c0eb2366c0a91 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 12 Jun 2006 23:59:16 +0000 Subject: [PATCH] Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register allocated, thus live across the save/reload. This fixes llc-beta /MultiSource/Applications/spiff/spiff llc-beta /MultiSource/Benchmarks/sim/sim: llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest: llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1 llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg and probably others, with -regalloc=local. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28761 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCRegisterInfo.cpp | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 7b9b8e7b611..8cc2da52fd3 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -102,20 +102,21 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); } else if (RC == PPC::CRRCRegisterClass) { + // FIXME: We use R0 here, because it isn't available for RA. // We need to store the CR in the low 4-bits of the saved value. First, // issue a MFCR to save all of the CRBits. - BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); + BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0); // If the saved register wasn't CR0, shift the bits left so that they are in // CR0's slot. if (SrcReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; - // rlwinm r11, r11, ShiftBits, 0, 31. - BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11) - .addReg(PPC::R11).addImm(ShiftBits).addImm(0).addImm(31); + // rlwinm r0, r0, ShiftBits, 0, 31. + BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) + .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); } - addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); + addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx); } else if (RC == PPC::GPRCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); } else if (RC == PPC::G8RCRegisterClass) { @@ -148,18 +149,19 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); } else if (RC == PPC::CRRCRegisterClass) { - addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); + // FIXME: We use R0 here, because it isn't available for RA. + addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx); // If the reloaded register isn't CR0, shift the bits right so that they are // in the right CR's slot. if (DestReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; // rlwinm r11, r11, 32-ShiftBits, 0, 31. - BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11) - .addReg(PPC::R11).addImm(32-ShiftBits).addImm(0).addImm(31); + BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) + .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); } - BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); + BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0); } else if (RC == PPC::GPRCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); } else if (RC == PPC::G8RCRegisterClass) { -- 2.34.1