From e68d16d33646fabf36e782b300404f112eb94d1d Mon Sep 17 00:00:00 2001 From: lintao Date: Wed, 24 Dec 2014 15:43:20 +0800 Subject: [PATCH] mmc: rk_sdmmc: manually zero desc after allocated on ARM64 platform. ARM64 call dmam_alloc_coherent mathod to allocate descriptor will not auto clear buffer. So mmc may get wrong d->desc1 calculated that load wrong address for BUF2 for dual-buf mode if NO CH set in d->desc0. Then IDMAC will halt for BUF2 in WR_REQ_WAIT state and cannot generate TI/RI or others in combine-interrupt. Signed-off-by: lintao --- drivers/mmc/host/rk_sdmmc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/rk_sdmmc.c b/drivers/mmc/host/rk_sdmmc.c index b6a18943df93..8f5fac19539a 100755 --- a/drivers/mmc/host/rk_sdmmc.c +++ b/drivers/mmc/host/rk_sdmmc.c @@ -3627,6 +3627,9 @@ static void dw_mci_init_dma(struct dw_mci *host) __func__); goto no_dma; } + #ifdef CONFIG_ARM64 + memset(host->sg_cpu, 0, PAGE_SIZE); + #endif /* Determine which DMA interface to use */ #if defined(CONFIG_MMC_DW_IDMAC) -- 2.34.1