From e699e95571e3c614b1cbf0aa95afd80aad4adac7 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Mon, 28 Feb 2005 17:22:18 +0000 Subject: [PATCH] fix integer division and stuff git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20372 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaInstrInfo.td | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index fdf6a9a2e02..7c736102e62 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -79,13 +79,13 @@ let Uses = [R29, R28] in { def STT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stt $RA,$DISP">; //store double } -let Uses = [R28, R23, R24, R25, R26, R29], - Defs = [R29] in +let Uses = [R29], + Defs = [R28, R29, R23, R24, R25, R27] in { def REMQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remqu $RA,$RB,$RC">; //unsigned remander - def REMQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remq $RA,$RB,$RC">; //unsigned remander - def DIVQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divqu $RA,$RB,$RC">; //unsigned remander - def DIVQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$RC">; //unsigned remander + def REMQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remq $RA,$RB,$RC">; //signed remander + def DIVQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divqu $RA,$RB,$RC">; //unsigned division + def DIVQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$RC">; //signed division } //*********************** -- 2.34.1