From e787ddb5105b2c355c166c395ddbeb2047cf3136 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Thu, 27 Jan 2011 21:28:51 +0000 Subject: [PATCH] Remove a temporary workaround for a lencod miscompile. Depends on the fix in r124442. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124443 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 87739c03914..ad835806a4e 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1645,13 +1645,11 @@ bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only // counts data deps. To be more precise, we could maintain a // NumDataSuccsLeft count. - /* FIXME: exposing a downstream bug, JM/lencode miscompile if (PredSU->NumSuccsLeft != PredSU->Succs.size()) { DEBUG(dbgs() << " SU(" << PredSU->NodeNum << ") live across SU(" << SU->NodeNum << ")\n"); continue; } - */ const SDNode *PN = PredSU->getNode(); if (!PN->isMachineOpcode()) { if (PN->getOpcode() == ISD::CopyFromReg) { -- 2.34.1