From e8ad273f980490245ac8c20b7ac691856c4c518f Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 7 Aug 2015 16:45:33 +0000 Subject: [PATCH] AMDGPU/SI: Use correct encoding of vopc for VI in the assembler Summary: We were using the SI encoding for VI. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11812 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244332 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIInstrInfo.td | 2 ++ test/MC/AMDGPU/vopc.s | 26 +++++++++++++++++--------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td index b90a53edbdd..7ecb25a52df 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.td +++ b/lib/Target/AMDGPU/SIInstrInfo.td @@ -1631,12 +1631,14 @@ multiclass VOPC_m pattern, SIMCInstr { let Defs = !if(DefExec, [EXEC], []); let hasSideEffects = DefExec; + let AssemblerPredicates = [isSICI]; } def _vi : VOPC, SIMCInstr { let Defs = !if(DefExec, [EXEC], []); let hasSideEffects = DefExec; + let AssemblerPredicates = [isVI]; } } diff --git a/test/MC/AMDGPU/vopc.s b/test/MC/AMDGPU/vopc.s index f44919a4f1e..2d8547c5f95 100644 --- a/test/MC/AMDGPU/vopc.s +++ b/test/MC/AMDGPU/vopc.s @@ -1,5 +1,6 @@ -// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s -// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI +// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI //===----------------------------------------------------------------------===// // Generic Checks @@ -7,23 +8,28 @@ // src0 sgpr v_cmp_lt_f32 vcc, s2, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c] // src0 inline immediate v_cmp_lt_f32 vcc, 0, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x02,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x02,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c] // src0 literal v_cmp_lt_f32 vcc, 10.0, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x02,0x7c,0x00,0x00,0x20,0x41] +// SICI: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x02,0x7c,0x00,0x00,0x20,0x41] +// VI: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x82,0x7c,0x00,0x00,0x20,0x41] // src0, src1 max vgpr v_cmp_lt_f32 vcc, v255, v255 -// CHECK: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c] // force 32-bit encoding v_cmp_lt_f32_e32 vcc, v2, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c] //===----------------------------------------------------------------------===// @@ -31,10 +37,12 @@ v_cmp_lt_f32_e32 vcc, v2, v4 //===----------------------------------------------------------------------===// v_cmp_f_f32 vcc, v2, v4 -// CHECK: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7c] +// SICI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7c] +// VI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c] v_cmp_lt_f32 vcc, v2, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c] // TODO: Add tests for the rest of the instructions. -- 2.34.1