From e9e26116cf21957e5027efd60be5b5393406fbd1 Mon Sep 17 00:00:00 2001 From: xxx Date: Mon, 8 Dec 2014 21:02:39 -0800 Subject: [PATCH] uart support 1m or 3M --- arch/arm/mach-rk30/clock_data.c | 14 +++++++------- arch/arm/mach-rk30/include/mach/board.h | 9 +++++++++ 2 files changed, 16 insertions(+), 7 deletions(-) mode change 100644 => 100755 arch/arm/mach-rk30/include/mach/board.h diff --git a/arch/arm/mach-rk30/clock_data.c b/arch/arm/mach-rk30/clock_data.c index 340b86028f3f..c95809aabbe1 100644 --- a/arch/arm/mach-rk30/clock_data.c +++ b/arch/arm/mach-rk30/clock_data.c @@ -42,6 +42,8 @@ #define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2) #define CLK_FLG_MAX_I2S_24576KHZ (1<<3) #define CLK_FLG_MAX_I2S_49152KHZ (1<<4) +//uart 1m\3m +#define CLK_FLG_UART_1_3M (1<<5) @@ -1081,6 +1083,7 @@ static const struct pll_clk_set cpll_clks[] = { _PLL_SET_CLKS(552000, 1, 23, 1), _PLL_SET_CLKS(600000, 1, 25, 1), _PLL_SET_CLKS(742500, 8, 495, 2), + _PLL_SET_CLKS(768000, 1, 32, 1), _PLL_SET_CLKS(798000, 4, 133, 1), _PLL_SET_CLKS(1188000,2, 99, 1), _PLL_SET_CLKS( 0, 4, 133, 1), @@ -1784,8 +1787,6 @@ static int clk_uart_set_rate(struct clk *clk, unsigned long rate) parent = clk->parents[UART_SRC_FRAC]; } - - CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n", clk->name,rate,parent->name,clk->parent->name); @@ -3303,11 +3304,10 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate); // uart - #if 0 - clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk); - #else - clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk); - #endif + if(rk30_clock_flags&CLK_FLG_UART_1_3M) + clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk); + else + clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk); //mac if(!(gpll_rate%(50*MHZ))) clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk); diff --git a/arch/arm/mach-rk30/include/mach/board.h b/arch/arm/mach-rk30/include/mach/board.h old mode 100644 new mode 100755 index d2a17e483efe..f23e46519265 --- a/arch/arm/mach-rk30/include/mach/board.h +++ b/arch/arm/mach-rk30/include/mach/board.h @@ -114,6 +114,7 @@ enum _codec_pll { codec_pll_552mhz = 552000000, /* for HDMI */ codec_pll_600mhz = 600000000, codec_pll_742_5khz = 742500000, + codec_pll_768mhz = 768000000, codec_pll_798mhz = 798000000, codec_pll_1188mhz = 1188000000, }; @@ -125,6 +126,8 @@ enum _codec_pll { #define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2) #define CLK_FLG_MAX_I2S_24576KHZ (1<<3) #define CLK_FLG_MAX_I2S_49152KHZ (1<<4) +//uart 1m\3m +#define CLK_FLG_UART_1_3M (1<<5) @@ -136,8 +139,14 @@ enum _codec_pll { #else + #define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/) + +#if (RK30_CLOCKS_DEFAULT_FLAGS&CLK_FLG_UART_1_3M) +#define codec_pll_default codec_pll_768mhz +#else #define codec_pll_default codec_pll_798mhz +#endif #define periph_pll_default periph_pll_297mhz #endif -- 2.34.1