From eb7e8235cf8d96fcd55af697cf72256892b303fd Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=99=88=E4=BA=AE?= Date: Thu, 18 Sep 2014 02:32:51 -0700 Subject: [PATCH] rk312x: correct clk_ddr rate MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: 陈亮 --- arch/arm/boot/dts/rk312x-clocks.dtsi | 2 +- arch/arm/mach-rockchip/ddr_freq.c | 10 ++++++++-- arch/arm/mach-rockchip/dvfs.c | 19 ++++++++++--------- drivers/clk/rockchip/clk-ops.c | 19 +++++++++++++++++++ include/dt-bindings/clock/rockchip.h | 1 + 5 files changed, 39 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/rk312x-clocks.dtsi b/arch/arm/boot/dts/rk312x-clocks.dtsi index a2c62f302b79..00f6af51ec88 100755 --- a/arch/arm/boot/dts/rk312x-clocks.dtsi +++ b/arch/arm/boot/dts/rk312x-clocks.dtsi @@ -1206,7 +1206,7 @@ #clock-cells = <0>; rockchip,flags = <(CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)>; - rockchip,clkops-idx = ; + rockchip,clkops-idx = ; }; /* reg[7:2]: reserved */ diff --git a/arch/arm/mach-rockchip/ddr_freq.c b/arch/arm/mach-rockchip/ddr_freq.c index dd09a5b30735..982971522045 100644 --- a/arch/arm/mach-rockchip/ddr_freq.c +++ b/arch/arm/mach-rockchip/ddr_freq.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "../../../drivers/clk/rockchip/clk-pd.h" #include "cpu_axi.h" @@ -912,8 +913,13 @@ static int ddrfreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate) real_rate *= MHZ; if (!real_rate) return -EAGAIN; - - clk->parent->rate = clk->rate = real_rate; + if (cpu_is_rk312x()) { + clk->parent->rate = 2 * real_rate; + clk->rate = real_rate; + } else { + clk->rate = real_rate; + clk->parent->rate = real_rate; + } return 0; } diff --git a/arch/arm/mach-rockchip/dvfs.c b/arch/arm/mach-rockchip/dvfs.c index ba676f686464..ea62aa4d6cd9 100644 --- a/arch/arm/mach-rockchip/dvfs.c +++ b/arch/arm/mach-rockchip/dvfs.c @@ -1028,9 +1028,10 @@ int dvfs_clk_enable_limit(struct dvfs_node *clk_dvfs_node, unsigned int min_rate } - DVFS_DBG("%s:clk(%s) last_set_rate=%u; [min_rate, max_rate]=[%u, %u]\n", - __func__, __clk_get_name(clk_dvfs_node->clk), clk_dvfs_node->last_set_rate, - clk_dvfs_node->min_rate, clk_dvfs_node->max_rate); + DVFS_DBG("%s:clk(%s) last_set_rate=%lu; [min_rate, max_rate]=[%u, %u]\n", + __func__, __clk_get_name(clk_dvfs_node->clk), + clk_dvfs_node->last_set_rate, + clk_dvfs_node->min_rate, clk_dvfs_node->max_rate); return 0; } @@ -1054,8 +1055,11 @@ int dvfs_clk_disable_limit(struct dvfs_node *clk_dvfs_node) mutex_unlock(&clk_dvfs_node->vd->mutex); } - DVFS_DBG("%s: clk(%s) last_set_rate=%u; [min_rate, max_rate]=[%u, %u]\n", - __func__, __clk_get_name(clk_dvfs_node->clk), clk_dvfs_node->last_set_rate, clk_dvfs_node->min_rate, clk_dvfs_node->max_rate); + DVFS_DBG("%s: clk(%s) last_set_rate=%lu; [min_rate, max_rate]=[%u, %u]\n", + __func__, __clk_get_name(clk_dvfs_node->clk), + clk_dvfs_node->last_set_rate, + clk_dvfs_node->min_rate, clk_dvfs_node->max_rate); + return 0; } EXPORT_SYMBOL(dvfs_clk_disable_limit); @@ -1329,11 +1333,8 @@ static int dvfs_target(struct dvfs_node *clk_dvfs_node, unsigned long rate) if (!clk) return -EINVAL; - if (!clk_dvfs_node->enable_count){ - DVFS_WARNING("%s:dvfs(%s) is disable\n", - __func__, clk_dvfs_node->name); + if (!clk_dvfs_node->enable_count) return 0; - } if (clk_dvfs_node->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) { /* It means the last time set voltage error */ diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c index 7107134a8e7e..197051dec37e 100644 --- a/drivers/clk/rockchip/clk-ops.c +++ b/drivers/clk/rockchip/clk-ops.c @@ -476,6 +476,24 @@ const struct clk_ops clkops_rate_ddr = { .determine_rate = clk_ddr_determine_rate, }; +static unsigned long clk_ddr_div2_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* Same as clk_core, we should NOT set clk_ddr's parent + * (dpll) rate directly as a side effect. + */ + struct clk *parent = __clk_get_parent(hw->clk); + + return clk_divider_recalc_rate(hw, __clk_get_rate(parent))/2; +} + +const struct clk_ops clkops_rate_ddr_div2 = { + .recalc_rate = clk_ddr_div2_recalc_rate, + .round_rate = clk_ddr_round_rate, + .set_rate = clk_ddr_set_rate, + .determine_rate = clk_ddr_determine_rate, +}; + static unsigned long clk_3288_i2s_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -692,6 +710,7 @@ struct clk_ops_table rk_clkops_rate_table[] = { {.index = CLKOPS_RATE_RK3288_USB480M, .clk_ops = &clkops_rate_3288_usb480m}, {.index = CLKOPS_RATE_RK3288_DCLK_LCDC0,.clk_ops = &clkops_rate_3288_dclk_lcdc0}, {.index = CLKOPS_RATE_RK3288_DCLK_LCDC1,.clk_ops = &clkops_rate_3288_dclk_lcdc1}, + {.index = CLKOPS_RATE_DDR_DIV2, .clk_ops = &clkops_rate_ddr_div2}, {.index = CLKOPS_RATE_I2S, .clk_ops = NULL}, {.index = CLKOPS_RATE_CIFOUT, .clk_ops = NULL}, {.index = CLKOPS_RATE_UART, .clk_ops = NULL}, diff --git a/include/dt-bindings/clock/rockchip.h b/include/dt-bindings/clock/rockchip.h index 8b9bc21e0e7e..5c1234e967e3 100644 --- a/include/dt-bindings/clock/rockchip.h +++ b/include/dt-bindings/clock/rockchip.h @@ -63,6 +63,7 @@ #define CLKOPS_RATE_RK3288_USB480M 15 #define CLKOPS_RATE_RK3288_DCLK_LCDC0 16 #define CLKOPS_RATE_RK3288_DCLK_LCDC1 17 +#define CLKOPS_RATE_DDR_DIV2 18 #define CLKOPS_TABLE_END (~0) /* pd id */ -- 2.34.1