From ebbbfd0e2eeeb5b1a15f0e655a0a2119510713d4 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 27 Jun 2011 19:24:13 +0000 Subject: [PATCH] More refactoring. MC doesn't need know about subreg indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133927 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/RegisterInfoEmitter.cpp | 157 +++++++++++++------------ utils/TableGen/RegisterInfoEmitter.h | 10 +- 2 files changed, 85 insertions(+), 82 deletions(-) diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index de20fb29b37..ab081eb013a 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -53,24 +53,8 @@ RegisterInfoEmitter::runEnums(raw_ostream &OS, if (!Namespace.empty()) OS << "}\n"; - const std::vector &SubRegIndices = Bank.getSubRegIndices(); - if (!SubRegIndices.empty()) { - OS << "\n// Subregister indices\n"; - Namespace = SubRegIndices[0]->getValueAsString("Namespace"); - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; - OS << "enum {\n NoSubRegister,\n"; - for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i) - OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; - OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; - OS << "};\n"; - if (!Namespace.empty()) - OS << "}\n"; - } - const std::vector &RegisterClasses = Target.getRegisterClasses(); - if (!RegisterClasses.empty()) { OS << "\n// Register classes\n"; OS << "namespace " << RegisterClasses[0].Namespace << " {\n"; @@ -88,67 +72,6 @@ RegisterInfoEmitter::runEnums(raw_ostream &OS, OS << "#endif // GET_REGINFO_ENUM\n\n"; } -void RegisterInfoEmitter::runHeader(raw_ostream &OS, CodeGenTarget &Target) { - EmitSourceFileHeader("Register Information Header Fragment", OS); - - OS << "\n#ifdef GET_REGINFO_HEADER\n"; - OS << "#undef GET_REGINFO_HEADER\n"; - - const std::string &TargetName = Target.getName(); - std::string ClassName = TargetName + "GenRegisterInfo"; - - OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; - OS << "#include \n\n"; - - OS << "namespace llvm {\n\n"; - - OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" - << " explicit " << ClassName - << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, " - << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" - << " virtual int getDwarfRegNumFull(unsigned RegNum, " - << "unsigned Flavour) const;\n" - << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " - << "unsigned Flavour) const;\n" - << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" - << " virtual bool needsStackRealignment(const MachineFunction &) const\n" - << " { return false; }\n" - << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" - << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n" - << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" - << "};\n\n"; - - const std::vector &RegisterClasses = - Target.getRegisterClasses(); - - if (!RegisterClasses.empty()) { - OS << "namespace " << RegisterClasses[0].Namespace - << " { // Register classes\n"; - - for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { - const CodeGenRegisterClass &RC = RegisterClasses[i]; - const std::string &Name = RC.getName(); - - // Output the register class definition. - OS << " struct " << Name << "Class : public TargetRegisterClass {\n" - << " " << Name << "Class();\n"; - if (!RC.AltOrderSelect.empty()) - OS << " ArrayRef " - "getRawAllocationOrder(const MachineFunction&) const;\n"; - OS << " };\n"; - - // Output the extern for the instance. - OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; - // Output the extern for the pointer to the instance (should remove). - OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" - << Name << "RegClass;\n"; - } - OS << "} // end of namespace " << TargetName << "\n\n"; - } - OS << "} // End llvm namespace \n"; - OS << "#endif // GET_REGINFO_HEADER\n\n"; -} - // // runMCDesc - Print out MC register descriptions. // @@ -255,6 +178,84 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "#endif // GET_REGINFO_MC_DESC\n\n"; } +void +RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, + CodeGenRegBank &RegBank) { + EmitSourceFileHeader("Register Information Header Fragment", OS); + + OS << "\n#ifdef GET_REGINFO_HEADER\n"; + OS << "#undef GET_REGINFO_HEADER\n"; + + const std::string &TargetName = Target.getName(); + std::string ClassName = TargetName + "GenRegisterInfo"; + + OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; + OS << "#include \n\n"; + + OS << "namespace llvm {\n\n"; + + OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" + << " explicit " << ClassName + << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, " + << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" + << " virtual int getDwarfRegNumFull(unsigned RegNum, " + << "unsigned Flavour) const;\n" + << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " + << "unsigned Flavour) const;\n" + << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" + << " virtual bool needsStackRealignment(const MachineFunction &) const\n" + << " { return false; }\n" + << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" + << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n" + << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" + << "};\n\n"; + + const std::vector &SubRegIndices = RegBank.getSubRegIndices(); + if (!SubRegIndices.empty()) { + OS << "\n// Subregister indices\n"; + std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace"); + if (!Namespace.empty()) + OS << "namespace " << Namespace << " {\n"; + OS << "enum {\n NoSubRegister,\n"; + for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i) + OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; + OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; + OS << "};\n"; + if (!Namespace.empty()) + OS << "}\n"; + } + + const std::vector &RegisterClasses = + Target.getRegisterClasses(); + + if (!RegisterClasses.empty()) { + OS << "namespace " << RegisterClasses[0].Namespace + << " { // Register classes\n"; + + for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { + const CodeGenRegisterClass &RC = RegisterClasses[i]; + const std::string &Name = RC.getName(); + + // Output the register class definition. + OS << " struct " << Name << "Class : public TargetRegisterClass {\n" + << " " << Name << "Class();\n"; + if (!RC.AltOrderSelect.empty()) + OS << " ArrayRef " + "getRawAllocationOrder(const MachineFunction&) const;\n"; + OS << " };\n"; + + // Output the extern for the instance. + OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; + // Output the extern for the pointer to the instance (should remove). + OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" + << Name << "RegClass;\n"; + } + OS << "} // end of namespace " << TargetName << "\n\n"; + } + OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_HEADER\n\n"; +} + // // runTargetDesc - Output the target register and register file descriptions. // @@ -748,7 +749,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegBank.computeDerivedInfo(); runEnums(OS, Target, RegBank); - runHeader(OS, Target); runMCDesc(OS, Target, RegBank); + runTargetHeader(OS, Target, RegBank); runTargetDesc(OS, Target, RegBank); } diff --git a/utils/TableGen/RegisterInfoEmitter.h b/utils/TableGen/RegisterInfoEmitter.h index d625b7d39a6..2c01b5c3bd0 100644 --- a/utils/TableGen/RegisterInfoEmitter.h +++ b/utils/TableGen/RegisterInfoEmitter.h @@ -31,14 +31,16 @@ public: // runEnums - Print out enum values for all of the registers. void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); - // runHeader - Emit a header fragment for the register info emitter. - void runHeader(raw_ostream &o, CodeGenTarget &Target); - // runMCDesc - Print out MC register descriptions. void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); + // runTargetHeader - Emit a header fragment for the register info emitter. + void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, + CodeGenRegBank &Bank); + // runTargetDesc - Output the target register and register file descriptions. - void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); + void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, + CodeGenRegBank &Bank); // run - Output the register file description. void run(raw_ostream &o); -- 2.34.1