From ec689151f29d328e9edcea2740c3a1d978aab6a6 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Mon, 14 Dec 2009 21:51:34 +0000 Subject: [PATCH] Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate between BR_JTr and STREXD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91339 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 4527a90b326..e14696a140d 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -786,6 +786,7 @@ let isBranch = 1, isTerminator = 1 in { def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), IIC_Br, "mov\tpc, $target \n$jt", [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { + let Inst{11-4} = 0b00000000; let Inst{15-12} = 0b1111; let Inst{20} = 0; // S Bit let Inst{24-21} = 0b1101; -- 2.34.1