From ec6fcdf62924201dd278b2ad0c374b13ebc1cd12 Mon Sep 17 00:00:00 2001 From: Xiao Feng Date: Tue, 23 Jun 2015 21:00:32 +0800 Subject: [PATCH] arm64: rockchip: rk3368-p9: dts: modify clocks init rate reduce aclk_bus hclk_bus aclk_peri hclk_peri for power Signed-off-by: Xiao Feng --- arch/arm64/boot/dts/rk3368-p9_818.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) mode change 100755 => 100644 arch/arm64/boot/dts/rk3368-p9_818.dts diff --git a/arch/arm64/boot/dts/rk3368-p9_818.dts b/arch/arm64/boot/dts/rk3368-p9_818.dts old mode 100755 new mode 100644 index 5a7a72c84e46..ba775d3f0c4a --- a/arch/arm64/boot/dts/rk3368-p9_818.dts +++ b/arch/arm64/boot/dts/rk3368-p9_818.dts @@ -742,3 +742,23 @@ reg = <0x00000000 0x00000000>; /* 0MB */ }; +&rockchip_clocks_init { + rockchip,clocks-init-rate = + <&clk_gpll 576000000>, <&clk_core_b 792000000>, + <&clk_core_l 600000000>, <&clk_cpll 400000000>, + /*<&clk_npll 500000000>,*/ <&aclk_bus 150000000>, + <&hclk_bus 75000000>, <&pclk_bus 75000000>, + <&clk_crypto 150000000>, <&aclk_peri 150000000>, + <&hclk_peri 75000000>, <&pclk_peri 75000000>, + <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>, + <&clk_cs 300000000>, <&clkin_trace 300000000>, + <&aclk_cci 600000000>, <&clk_mac 125000000>, + <&aclk_vio0 400000000>, <&hclk_vio 100000000>, + <&aclk_rga_pre 400000000>, <&clk_rga 400000000>, + <&clk_isp 400000000>, <&clk_edp 200000000>, + <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>, + <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>, + <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>, + <&clk_hevc_cabac 300000000>; +}; + -- 2.34.1