From ece90bb19e8f13f24158cb096bed0e7161e294a6 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 30 Jul 2015 17:03:11 +0000 Subject: [PATCH] AMDGPU: Set SubRegIndex size and offset I'm not sure what reasons the comment here could have had for not setting these. Without these set, there is an assertion hit during DWARF emission. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243661 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPURegisterInfo.td | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPURegisterInfo.td b/lib/Target/AMDGPU/AMDGPURegisterInfo.td index 835a1464395..ba0490abee8 100644 --- a/lib/Target/AMDGPU/AMDGPURegisterInfo.td +++ b/lib/Target/AMDGPU/AMDGPURegisterInfo.td @@ -14,8 +14,7 @@ let Namespace = "AMDGPU" in { foreach Index = 0-15 in { - // Indices are used in a variety of ways here, so don't set a size/offset. - def sub#Index : SubRegIndex<-1, -1>; + def sub#Index : SubRegIndex<32, !shl(Index, 5)>; } def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">; -- 2.34.1