From ed83a7019be05c2ed16a134fc9a708eb25dcd641 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 7 Oct 2006 00:58:36 +0000 Subject: [PATCH] Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom part was always forced to be sextload, even when we needed an zextload. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30782 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index fc14b062aae..71f1c2449ea 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -4474,13 +4474,12 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ SDOperand Chain = Node->getOperand(0); SDOperand Ptr = Node->getOperand(1); MVT::ValueType EVT = cast(Node->getOperand(3))->getVT(); - unsigned LType = Node->getConstantOperandVal(4); + ISD::LoadExtType LType = (ISD::LoadExtType)Node->getConstantOperandVal(4); if (EVT == NVT) Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); else - Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), - EVT); + Lo = DAG.getExtLoad(LType, NVT, Chain, Ptr, Node->getOperand(2), EVT); // Remember that we legalized the chain. AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); -- 2.34.1