From edd4032b64387de794829861fb20792011e948d6 Mon Sep 17 00:00:00 2001
From: WeiYong Bi <bivvy.bi@rock-chips.com>
Date: Wed, 15 Mar 2017 09:07:51 +0800
Subject: [PATCH] ARM64: dts: rk3368: Add MIPI DSI support

Change-Id: Ia74bb0726cb23acc914f976acf76849f0e764280
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 48 ++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index a6b3b0c1cb26..39ba7d713bde 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -48,6 +48,9 @@
 #include <dt-bindings/power/rk3368-power.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/display/mipi_dsi.h>
+#include <dt-bindings/display/drm_mipi_dsi.h>
+#include <dt-bindings/display/media-bus-format.h>
 
 / {
 	compatible = "rockchip,rk3368";
@@ -1148,6 +1151,11 @@
 		vop_out: port {
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			vop_out_mipi: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi_in_vop>;
+			};
 		};
 	};
 
@@ -1169,6 +1177,46 @@
 		status = "disabled";
 	};
 
+	mipi_dsi_host: mipi-dsi-host@ff960000 {
+		compatible = "rockchip,rk3368-mipi-dsi";
+		reg = <0x0 0xff960000 0x0 0x4000>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_MIPI_DSI0>;
+		clock-names = "pclk";
+		phys = <&mipi_dphy>;
+		phy-names = "mipi_dphy";
+		rockchip,grf = <&grf>;
+		power-domains = <&power RK3368_PD_VIO>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		ports@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			mipi_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mipi_in_vop: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vop_out_mipi>;
+				};
+			};
+		};
+	};
+
+	mipi_dphy: mipi-dphy@ff968000 {
+		compatible = "rockchip,rk3368-mipi-dphy";
+		reg = <0x0 0xff968000 0x0 0x4000>;
+		#phy-cells = <0>;
+		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
+		clock-names = "ref", "pclk";
+		status = "disabled";
+	};
+
 	hevc_mmu: iommu@ff9a0440 {
 		compatible = "rockchip,iommu";
 		reg = <0x0 0xff9a0440 0x0 0x100>,
-- 
2.34.1