From edf2e8da256496c19390cfd46da80746373e9989 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 6 Mar 2007 20:01:06 +0000 Subject: [PATCH] big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not the lo-reg first. This is fallout from my ppc calling conv change yesterday, it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34983 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 84a381bf633..8c90cfb6dac 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1675,6 +1675,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { if (Tmp2.getValueType() != MVT::Vector) { SDOperand Lo, Hi; ExpandOp(Tmp2, Lo, Hi); + + // Big endian systems want the hi reg first. + if (!TLI.isLittleEndian()) + std::swap(Lo, Hi); + if (Hi.Val) Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); else -- 2.34.1