From ee10ab5e955e8d87778ff2d7e7ca79d82dd6c5b5 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Mon, 2 Nov 2015 14:01:11 +0000 Subject: [PATCH] Fix for bootstrap bug introduced in r244921 This revision has introduced an issue that only affects bootstrapped compiler when it is printing the ASM. It turns out that the new code path taken due to legalizing a scalar_to_vector of i64 -> v2i64 exposes a missing check in a micro optimization to change a load followed by a scalar_to_vector into a load and splat instruction on PPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251798 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 2 +- lib/Target/PowerPC/PPCISelLowering.cpp | 3 +-- .../PowerPC/p8-scalar_vector_conversions.ll | 23 ++++++++++++++++--- test/CodeGen/PowerPC/vsx.ll | 16 ++++++------- 4 files changed, 30 insertions(+), 14 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 1a0fe7954e4..908a365f9ef 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -2798,7 +2798,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) { LoadSDNode *LD = cast(Op1.getOperand(0)); SDValue Base, Offset; - if (LD->isUnindexed() && + if (LD->isUnindexed() && LD->hasOneUse() && Op1.hasOneUse() && (LD->getMemoryVT() == MVT::f64 || LD->getMemoryVT() == MVT::i64) && SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) { diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 8b55791f7e9..f4919dd9acc 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -552,8 +552,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal); - // FIXME: this is causing bootstrap failures, disable temporarily - //setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal); + setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); diff --git a/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll index 5f25139140f..35d501e40cb 100644 --- a/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll +++ b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -5,6 +5,8 @@ ; direct moves. This corresponds to the "insertelement" instruction. Subsequent ; to this, there will be a splat corresponding to the shufflevector. +@d = common global double 0.000000e+00, align 8 + ; Function Attrs: nounwind define <16 x i8> @buildc(i8 zeroext %a) { entry: @@ -59,9 +61,9 @@ entry: %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer ret <2 x i64> %splat.splat -; FIXME-CHECK: mtvsrd {{[0-9]+}}, 3 -; FIXME-CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 -; FIXME-CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +; CHECK: mtvsrd {{[0-9]+}}, 3 +; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 +; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] } ; Function Attrs: nounwind @@ -78,6 +80,21 @@ entry: ; CHECK-LE: xxsldwi {{[0-9]+}}, [[REG1]], [[REG1]], 1 } +; The optimization to remove stack operations from PPCDAGToDAGISel::Select +; should still trigger for v2f64, producing an lxvdsx. +; Function Attrs: nounwind +define <2 x double> @buildd() #0 { +entry: + %0 = load double, double* @d, align 8 + %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0 + %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer + ret <2 x double> %splat.splat +; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l +; CHECK: lxvdsx 34, 0, [[REG1]] +; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l +; CHECK-LE: lxvdsx 34, 0, [[REG1]] +} + ; Function Attrs: nounwind define signext i8 @getsc0(<16 x i8> %vsc) { entry: diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index 3820e19c077..b4b1d248d1a 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -1226,14 +1226,14 @@ define <2 x i32> @test80(i32 %v) { ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test80 -; FIXME-CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3 -; FIXME-CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI -; FIXME-CHECK-LE-DAG: xxswapd [[V1:[0-9]+]], [[R1]] -; FIXME-CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]] -; FIXME-CHECK-LE-DAG: xxspltd 34, [[V1]] -; FIXME-CHECK-LE-DAG: xxswapd 35, [[V2]] -; FIXME-CHECK-LE: vaddudm 2, 2, 3 -; FIXME-CHECK-LE: blr +; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3 +; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI +; CHECK-LE-DAG: xxswapd [[V1:[0-9]+]], [[R1]] +; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]] +; CHECK-LE-DAG: xxspltd 34, [[V1]] +; CHECK-LE-DAG: xxswapd 35, [[V2]] +; CHECK-LE: vaddudm 2, 2, 3 +; CHECK-LE: blr } define <2 x double> @test81(<4 x float> %b) { -- 2.34.1