From ee4021af68b35898309c77bafad3069445f0246b Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Wed, 25 May 2016 16:51:56 +0800 Subject: [PATCH] UPSTREAM: clk: rockchip: add a dummy clock for the watchdog pclk on rk3399 Like rk3288, the pclk supplying the watchdog is controlled via the SGRF register area. Additionally the SGRF isn't even writable in every boot mode. But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate. Signed-off-by: Xing Zheng Reviewed-by: Stephen Barber Signed-off-by: Heiko Stuebner (cherry picked from commit git.kernel.org mmind/linux-rockchip.git volatile-v4.8-clk/next e3d86c1a2295184374cf25cdb525e68a93b0ff90) Change-Id: I616846d389d324be529966c63820e8707c7d428f Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3399.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 12a8021a99a5..506c9ec79547 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1558,6 +1558,7 @@ static void __init rk3399_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk *clk; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -1571,6 +1572,14 @@ static void __init rk3399_clk_init(struct device_node *np) return; } + /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ + clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock pclk_wdt: %ld\n", + __func__, PTR_ERR(clk)); + else + rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); + rockchip_clk_register_plls(ctx, rk3399_pll_clks, ARRAY_SIZE(rk3399_pll_clks), -1); -- 2.34.1