From ee563cb978c8704a3020fc04d76468f625c572c4 Mon Sep 17 00:00:00 2001 From: Misha Brukman Date: Wed, 21 May 2003 17:59:06 +0000 Subject: [PATCH] Namespacified `vector' and `cerr' to always use the `std::' namespace. Eliminated `using' directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6261 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SparcV9/SparcV9InstrSelection.cpp | 35 +++---- lib/Target/SparcV9/SparcV9RegClassInfo.cpp | 38 ++++--- lib/Target/SparcV9/SparcV9RegInfo.cpp | 105 +++++++++---------- 3 files changed, 90 insertions(+), 88 deletions(-) diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp index 1826fbd4cfb..9b3e38a49df 100644 --- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp +++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp @@ -24,10 +24,9 @@ #include "llvm/ConstantHandling.h" #include "Support/MathExtras.h" #include -using std::vector; static inline void Add3OperandInstr(unsigned Opcode, InstructionNode* Node, - vector& mvec) { + std::vector& mvec) { mvec.push_back(BuildMI(Opcode, 3).addReg(Node->leftChild()->getValue()) .addReg(Node->rightChild()->getValue()) .addRegDef(Node->getValue())); @@ -73,7 +72,7 @@ IsZero(Value* idx) } static Value* -FoldGetElemChain(InstrTreeNode* ptrNode, vector& chainIdxVec, +FoldGetElemChain(InstrTreeNode* ptrNode, std::vector& chainIdxVec, bool lastInstHasLeadingNonZero) { InstructionNode* gepNode = dyn_cast(ptrNode); @@ -164,7 +163,7 @@ FoldGetElemChain(InstrTreeNode* ptrNode, vector& chainIdxVec, static Value * GetGEPInstArgs(InstructionNode* gepNode, - vector& idxVec, + std::vector& idxVec, bool& allConstantIndices) { allConstantIndices = true; @@ -221,7 +220,7 @@ GetGEPInstArgs(InstructionNode* gepNode, static Value* GetMemInstArgs(InstructionNode* memInstrNode, - vector& idxVec, + std::vector& idxVec, bool& allConstantIndices) { allConstantIndices = false; @@ -745,7 +744,7 @@ CreateShiftInstructions(const TargetMachine& target, Value* optArgVal2, /* Use optArgVal2 if not NULL */ unsigned optShiftNum, /* else use optShiftNum */ Instruction* destVal, - vector& mvec, + std::vector& mvec, MachineCodeForInstruction& mcfi) { assert((optArgVal2 != NULL || optShiftNum <= 64) && @@ -788,7 +787,7 @@ CreateShiftInstructions(const TargetMachine& target, static inline unsigned CreateMulConstInstruction(const TargetMachine &target, Function* F, Value* lval, Value* rval, Instruction* destVal, - vector& mvec, + std::vector& mvec, MachineCodeForInstruction& mcfi) { /* Use max. multiply cost, viz., cost of MULX */ @@ -869,7 +868,7 @@ CreateCheapestMulConstInstruction(const TargetMachine &target, Function* F, Value* lval, Value* rval, Instruction* destVal, - vector& mvec, + std::vector& mvec, MachineCodeForInstruction& mcfi) { Value* constOp; @@ -892,7 +891,7 @@ CreateCheapestMulConstInstruction(const TargetMachine &target, static inline void CreateMulInstruction(const TargetMachine &target, Function* F, Value* lval, Value* rval, Instruction* destVal, - vector& mvec, + std::vector& mvec, MachineCodeForInstruction& mcfi, MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE) { @@ -941,7 +940,7 @@ ChooseDivInstruction(TargetMachine &target, static inline void CreateDivConstInstruction(TargetMachine &target, const InstructionNode* instrNode, - vector& mvec) + std::vector& mvec) { Value* LHS = instrNode->leftChild()->getValue(); Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); @@ -1005,7 +1004,7 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target, Instruction* result, unsigned tsize, Value* numElementsVal, - vector& getMvec) + std::vector& getMvec) { Value* totalSizeVal; MachineInstr* M; @@ -1076,7 +1075,7 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target, Instruction* result, unsigned tsize, unsigned numElements, - vector& getMvec) + std::vector& getMvec) { assert(tsize > 0 && "Illegal (zero) type size for alloca"); assert(result && result->getParent() && @@ -1131,13 +1130,13 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target, static void SetOperandsForMemInstr(unsigned Opcode, - vector& mvec, + std::vector& mvec, InstructionNode* vmInstrNode, const TargetMachine& target) { Instruction* memInst = vmInstrNode->getInstruction(); // Index vector, ptr value, and flag if all indices are const. - vector idxVec; + std::vector idxVec; bool allConstantIndices; Value* ptrVal = GetMemInstArgs(vmInstrNode, idxVec, allConstantIndices); @@ -1176,7 +1175,7 @@ SetOperandsForMemInstr(unsigned Opcode, Value* idxVal = idxVec[firstIdxIsZero]; - vector mulVec; + std::vector mulVec; Instruction* addr = new TmpInstruction(Type::ULongTy, memInst); MachineCodeForInstruction::get(memInst).addTemp(addr); @@ -1366,7 +1365,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, int ruleForNode, short* nts, TargetMachine &target, - vector& mvec) + std::vector& mvec) { bool checkCast = false; // initialize here to use fall-through bool maskUnsignedResult = false; @@ -2171,7 +2170,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, intArgReg = new TmpInstruction(Type::IntTy, argVal); destMCFI.addTemp(intArgReg); - vector copyMvec; + std::vector copyMvec; target.getInstrInfo().CreateCodeToCopyFloatToInt(target, callInstr->getParent()->getParent(), argVal, (TmpInstruction*) intArgReg, @@ -2256,7 +2255,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum); else { - vector minstrVec; + std::vector minstrVec; Instruction* instr = subtreeRoot->getInstruction(); target.getInstrInfo(). CreateCopyInstructionsByType(target, diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp index 9da1d69e747..e8a63a81014 100644 --- a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp @@ -7,8 +7,6 @@ #include "SparcRegClassInfo.h" #include "llvm/Type.h" #include "../../CodeGen/RegAlloc/RegAllocCommon.h" // FIXME! -using std::cerr; -using std::vector; //----------------------------------------------------------------------------- // Int Register Class - method for coloring a node in the interference graph. @@ -23,11 +21,13 @@ using std::vector; // If both above fail, spill. // //----------------------------------------------------------------------------- -void SparcIntRegClass::colorIGNode(IGNode * Node, vector &IsColorUsedArr) const { +void SparcIntRegClass::colorIGNode(IGNode * Node, + std::vector &IsColorUsedArr) const +{ LiveRange *LR = Node->getParentLR(); if( DEBUG_RA ) { - cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:"; + std::cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:"; printSet(*LR); } @@ -43,18 +43,18 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, vector &IsColorUsedArr) // there are no call interferences. Otherwise, it will get spilled. if (DEBUG_RA) - cerr << "\n -Coloring with sug color: " << SugCol; + std::cerr << "\n -Coloring with sug color: " << SugCol; LR->setColor( LR->getSuggestedColor() ); return; } else if(DEBUG_RA) - cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf"; + std::cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf"; } - else if ( DEBUG_RA ) { // can't allocate the suggested col - cerr << " \n Could NOT allocate the suggested color (already used) "; - printSet(*LR); cerr << "\n"; + else if (DEBUG_RA) { // can't allocate the suggested col + std::cerr << "\n Could NOT allocate the suggested color (already used) "; + printSet(*LR); std::cerr << "\n"; } } @@ -81,7 +81,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, vector &IsColorUsedArr) if( ColorFound) { LR->setColor(c); // first color found in preffered order - if (DEBUG_RA) cerr << "\n Colored after first search with col " << c ; + if (DEBUG_RA) std::cerr << "\n Colored after first search with col " << c; } // if color is not found because of call interference @@ -103,7 +103,8 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, vector &IsColorUsedArr) // since LR span across calls, must save across calls // LR->markForSaveAcrossCalls(); - if(DEBUG_RA) cerr << "\n Colored after SECOND search with col " << c ; + if (DEBUG_RA) + std::cerr << "\n Colored after SECOND search with col " << c; } } @@ -136,7 +137,8 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, vector &IsColorUsedArr) // //---------------------------------------------------------------------------- void SparcFloatRegClass::colorIGNode(IGNode * Node, - vector &IsColorUsedArr) const{ + std::vector &IsColorUsedArr) const +{ LiveRange *LR = Node->getParentLR(); // Mark the second color for double-precision registers: @@ -172,8 +174,8 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node, LR->setColor( LR->getSuggestedColor() ); return; } else if (DEBUG_RA) { // can't allocate the suggested col - cerr << " Could NOT allocate the suggested color for LR "; - printSet(*LR); cerr << "\n"; + std::cerr << " Could NOT allocate the suggested color for LR "; + printSet(*LR); std::cerr << "\n"; } } @@ -247,9 +249,11 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node, // type of the Node (i.e., float/double) //----------------------------------------------------------------------------- -int SparcFloatRegClass::findFloatColor(const LiveRange *LR, - unsigned Start, unsigned End, - vector &IsColorUsedArr) const { +int SparcFloatRegClass::findFloatColor +(const LiveRange *LR, + unsigned Start, unsigned End, + std::vector &IsColorUsedArr) const +{ bool ColorFound = false; unsigned c; diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index 87493963655..1e5c09e56cf 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -19,8 +19,6 @@ #include "llvm/iOther.h" #include "llvm/Function.h" #include "llvm/DerivedTypes.h" -using std::cerr; -using std::vector; enum { BadRegClass = ~0 @@ -665,7 +663,7 @@ UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI, PhyRegAlloc &PRA, LiveRange* LR, unsigned regType, unsigned RegClassID, int UniArgRegOrNone, unsigned argNo, - std::vector& AddedInstrnsBefore) + std::vector &AddedInstrnsBefore) const { MachineInstr *AdMI; @@ -778,7 +776,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal ); if (!RetValLR) { - cerr << "\nNo LR for:" << RAV(RetVal) << "\n"; + std::cerr << "\nNo LR for:" << RAV(RetVal) << "\n"; assert(RetValLR && "ERR:No LR for non-void return value"); } @@ -840,7 +838,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, // Now color all args of the call instruction //------------------------------------------- - std::vector AddedInstrnsBefore; + std::vector AddedInstrnsBefore; unsigned NumOfCallArgs = argDesc->getNumArgs(); @@ -882,7 +880,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, // not possible to have a null LR since all args (even consts) // must be defined before if (!LR) { - cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) <<"\n"; + std::cerr <<" ERROR: In call instr, no LR for arg: " < ReorderedVec; + std::vector ReorderedVec; if (!AddedInstrnsBefore.empty()) { if (DEBUG_RA) { - cerr << "\nCalling reorder with instrns: \n"; + std::cerr << "\nCalling reorder with instrns: \n"; for(unsigned i=0; i < AddedInstrnsBefore.size(); i++) - cerr << *(AddedInstrnsBefore[i]); + std::cerr << *(AddedInstrnsBefore[i]); } OrderAddedInstrns(AddedInstrnsBefore, ReorderedVec, PRA); @@ -943,9 +941,9 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, && "Dropped some instructions when reordering!"); if (DEBUG_RA) { - cerr << "\nAfter reordering instrns: \n"; + std::cerr << "\nAfter reordering instrns: \n"; for(unsigned i = 0; i < ReorderedVec.size(); i++) - cerr << *ReorderedVec[i]; + std::cerr << *ReorderedVec[i]; } } @@ -980,7 +978,7 @@ void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI, LiveRange *const LR = LRI.getLiveRangeForValue( RetVal ); if (!LR) { - cerr << "\nNo LR for:" << RAV(RetVal) << "\n"; + std::cerr << "\nNo LR for:" << RAV(RetVal) << "\n"; assert(0 && "No LR for return value of non-void method"); } @@ -1015,7 +1013,7 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI, LiveRange *LR = LRI.getLiveRangeForValue(RetVal); if (!LR) { - cerr << "\nNo LR for:" << RAV(RetVal) << "\n"; + std::cerr << "\nNo LR for:" << RAV(RetVal) << "\n"; // assert( LR && "No LR for return value of non-void method"); return; } @@ -1060,7 +1058,7 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI, else { // if the LR is spilled cpMem2RegMI(RetAI->InstrnsBefore, getFramePointer(), LR->getSpillOffFromFP(), UniRetReg, regType); - //cerr << "\nCopied the return value from stack\n"; + //std::cerr << "\nCopied the return value from stack\n"; } } // if there is a return value @@ -1094,7 +1092,7 @@ UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType, //--------------------------------------------------------------------------- void -UltraSparcRegInfo::cpReg2RegMI(vector& mvec, +UltraSparcRegInfo::cpReg2RegMI(std::vector& mvec, unsigned SrcReg, unsigned DestReg, int RegType) const { @@ -1152,7 +1150,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector& mvec, void -UltraSparcRegInfo::cpReg2MemMI(vector& mvec, +UltraSparcRegInfo::cpReg2MemMI(std::vector& mvec, unsigned SrcReg, unsigned DestPtrReg, int Offset, int RegType, @@ -1206,7 +1204,7 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, void -UltraSparcRegInfo::cpMem2RegMI(vector& mvec, +UltraSparcRegInfo::cpMem2RegMI(std::vector& mvec, unsigned SrcPtrReg, int Offset, unsigned DestReg, @@ -1264,7 +1262,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, void UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest, - vector& mvec) const { + std::vector& mvec) const { int RegType = getRegType(Src->getType()); MachineInstr * MI = NULL; @@ -1306,11 +1304,12 @@ UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest, void -UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, - vector& instrnsAfter, - MachineInstr *CallMI, - const BasicBlock *BB, - PhyRegAlloc &PRA) const +UltraSparcRegInfo::insertCallerSavingCode +(std::vector &instrnsBefore, + std::vector &instrnsAfter, + MachineInstr *CallMI, + const BasicBlock *BB, + PhyRegAlloc &PRA) const { assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); @@ -1377,7 +1376,7 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, int StackOff = PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType)); - vector AdIBef, AdIAft; + std::vector AdIBef, AdIAft; //---- Insert code for pushing the reg on stack ---------- @@ -1439,11 +1438,11 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, PushedRegSet.insert(Reg); if(DEBUG_RA) { - cerr << "\nFor call inst:" << *CallMI; - cerr << " -inserted caller saving instrs: Before:\n\t "; + std::cerr << "\nFor call inst:" << *CallMI; + std::cerr << " -inserted caller saving instrs: Before:\n\t "; for_each(instrnsBefore.begin(), instrnsBefore.end(), std::mem_fun(&MachineInstr::dump)); - cerr << " -and After:\n\t "; + std::cerr << " -and After:\n\t "; for_each(instrnsAfter.begin(), instrnsAfter.end(), std::mem_fun(&MachineInstr::dump)); } @@ -1465,25 +1464,25 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, void UltraSparcRegInfo::printReg(const LiveRange *LR) { unsigned RegClassID = LR->getRegClassID(); - cerr << " *Node " << (LR->getUserIGNode())->getIndex(); + std::cerr << " *Node " << (LR->getUserIGNode())->getIndex(); if (!LR->hasColor()) { - cerr << " - could not find a color\n"; + std::cerr << " - could not find a color\n"; return; } // if a color is found - cerr << " colored with color "<< LR->getColor(); + std::cerr << " colored with color "<< LR->getColor(); if (RegClassID == IntRegClassID) { - cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n"; + std::cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n"; } else if (RegClassID == FloatRegClassID) { - cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor()); + std::cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor()); if( LR->getType() == Type::DoubleTy) - cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1); - cerr << "]\n"; + std::cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1); + std::cerr << "]\n"; } } @@ -1545,7 +1544,7 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, do { CouldMoveAll = true; - std::vector::iterator DefIt = UnordVec.begin(); + std::vector::iterator DefIt = UnordVec.begin(); for( ; DefIt != UnordVec.end(); ++DefIt ) { @@ -1555,7 +1554,7 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, if( DefInst == NULL) continue; - //cerr << "\nInst in UnordVec = " << *DefInst; + //std::cerr << "\nInst in UnordVec = " << *DefInst; // last operand is the def (unless for a store which has no def reg) MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1); @@ -1566,7 +1565,7 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, // If the operand in DefInst is a def ... bool DefEqUse = false; - std::vector::iterator UseIt = DefIt; + std::vector::iterator UseIt = DefIt; UseIt++; for( ; UseIt != UnordVec.end(); ++UseIt ) { @@ -1587,7 +1586,7 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, // if Def and this use are the same, it means that this use // is destroyed by a def before it is used - // cerr << "\nCouldn't move " << *DefInst; + // std::cerr << "\nCouldn't move " << *DefInst; DefEqUse = true; CouldMoveAll = false; @@ -1604,7 +1603,7 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, // after examining all the instructions that follow the DefInst // if there are no dependencies, we can move it to the OrdVec - // cerr << "Moved to Ord: " << *DefInst; + // std::cerr << "Moved to Ord: " << *DefInst; moveInst2OrdVec(OrdVec, DefInst, PRA); @@ -1623,9 +1622,9 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, } while(!CouldMoveAll); if (DebugPrint && DEBUG_RA) { - cerr << "\nAdded instructions were reordered to:\n"; + std::cerr << "\nAdded instructions were reordered to:\n"; for(unsigned i=0; i < OrdVec.size(); i++) - cerr << *OrdVec[i]; + std::cerr << *OrdVec[i]; } } @@ -1633,7 +1632,7 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, -void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, +void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, MachineInstr *UnordInst, PhyRegAlloc &PRA) const { MachineOperand& UseOp = UnordInst->getOperand(0); @@ -1645,7 +1644,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, // before in the OrdVec bool DefEqUse = false; - std::vector::iterator OrdIt = OrdVec.begin(); + std::vector::iterator OrdIt = OrdVec.begin(); for( ; OrdIt != OrdVec.end(); ++OrdIt ) { @@ -1657,7 +1656,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, if( DefOp.opIsDef() && DefOp.getType() == MachineOperand::MO_MachineRegister) { - //cerr << "\nDefining Ord Inst: " << *OrdInst; + //std::cerr << "\nDefining Ord Inst: " << *OrdInst; if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) { @@ -1678,9 +1677,9 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType)); // Save the UReg (%ox) on stack before it's destroyed - vector mvec; + std::vector mvec; cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType); - for (vector::iterator MI=mvec.begin(); + for (std::vector::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) OrdIt = 1+OrdVec.insert(OrdIt, *MI); @@ -1693,14 +1692,14 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType); if( DEBUG_RA ) { - cerr << "\nFixed CIRCULAR references by reordering:"; - cerr << "\nBefore CIRCULAR Reordering:\n"; - cerr << *UnordInst; - cerr << *OrdInst; + std::cerr << "\nFixed CIRCULAR references by reordering:"; + std::cerr << "\nBefore CIRCULAR Reordering:\n"; + std::cerr << *UnordInst; + std::cerr << *OrdInst; - cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n"; + std::cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n"; for(unsigned i=0; i < OrdVec.size(); i++) - cerr << *(OrdVec[i]); + std::cerr << *(OrdVec[i]); } // Do not copy the UseInst to OrdVec @@ -1717,7 +1716,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, // We didn't find a def in the OrdVec, so just append this inst OrdVec.push_back( UnordInst ); - //cerr << "Reordered Inst (Moved Dn): " << *UnordInst; + //std::cerr << "Reordered Inst (Moved Dn): " << *UnordInst; } }// if the operand in UnordInst is a use -- 2.34.1