From eec041a037a5dffadbc27af1d0e714e76079f06d Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 27 Apr 2007 07:50:02 +0000 Subject: [PATCH] Back out previous check-in. Incorrect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36503 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 56a2d9452d4..48196369add 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -56,10 +56,6 @@ class TIt pattern> class TIx2 pattern> : ThumbI; -// tLEApcrel and tLEApcrelJT -class TIsx2 pattern> - : ThumbI; - // BR_JT instructions class TJTI pattern> : ThumbI; @@ -513,14 +509,14 @@ let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler. // tLEApcrel - Load a pc-relative address into a register without offending the // assembler. -def tLEApcrel : TIsx2<(ops GPR:$dst, i32imm:$label), +def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label), !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", "${:private}PCRELL${:uid}+6))\n"), !strconcat("\tmov $dst, #PCRELV${:uid}\n", "${:private}PCRELL${:uid}:\n\tadd $dst, pc")), []>; -def tLEApcrelJT : TIsx2<(ops GPR:$dst, i32imm:$label, i32imm:$id), +def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id), !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", "${:private}PCRELL${:uid}+4))\n"), !strconcat("\tmov $dst, #PCRELV${:uid}\n", -- 2.34.1