From f030ff821d480685d63e7d7320f3d3646298e140 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Tue, 14 Mar 2017 14:42:59 +0800
Subject: [PATCH] arm64: dts: rockchip: modify cpu's opp table for rk3368
Change-Id: I2f7f15f9b3a9e6190e5e8895e9e4fe939d284b43
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 75 ++++++++++++++++++------
1 file changed, 56 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index fd06e6ca7c19..062b02fef10e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -128,7 +128,7 @@
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>; /* min followed by max */
};
@@ -140,7 +140,7 @@
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_l2: cpu@2 {
@@ -150,7 +150,7 @@
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_l3: cpu@3 {
@@ -160,7 +160,7 @@
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_b0: cpu@100 {
@@ -170,7 +170,7 @@
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>; /* min followed by max */
};
@@ -182,7 +182,7 @@
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_b2: cpu@102 {
@@ -192,7 +192,7 @@
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_b3: cpu@103 {
@@ -202,7 +202,7 @@
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
};
};
@@ -210,27 +210,36 @@
compatible = "operating-points-v2";
opp-shared;
+ opp@216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
opp@408000000 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
clock-latency-ns = <40000>;
- opp-suspend;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@816000000 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1025000 1025000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1125000 1125000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1225000 1225000 1350000>;
+ clock-latency-ns = <40000>;
};
};
@@ -238,23 +247,51 @@
compatible = "operating-points-v2";
opp-shared;
+ opp@216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
opp@408000000 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
clock-latency-ns = <40000>;
- opp-suspend;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@816000000 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <975000 975000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1050000 1050000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1150000 1150000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1225000 1225000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1300000 1300000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ clock-latency-ns = <40000>;
};
};
--
2.34.1