From f051c1a29dd040b4b5ca0c5696d47a9058f87481 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 18 Apr 2011 07:00:40 +0000 Subject: [PATCH] while we're at it, handle 'sdiv exact' of a power of 2 also, this fixes a few rejects on c++ iterator loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129694 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/FastISel.cpp | 8 ++++++++ test/CodeGen/X86/fast-isel-x86-64.ll | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index d3a721f8754..76e9a7cac2d 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -360,6 +360,14 @@ bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) { if (ConstantInt *CI = dyn_cast(I->getOperand(1))) { uint64_t Imm = CI->getZExtValue(); + // Transform "sdiv exact X, 8" -> "sra X, 3". + if (ISDOpcode == ISD::SDIV && isa(I) && + cast(I)->isExact() && + isPowerOf2_64(Imm)) { + Imm = Log2_64(Imm); + ISDOpcode = ISD::SRA; + } + unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Op0IsKill, Imm, VT.getSimpleVT()); if (ResultReg == 0) return false; diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll index dbf65f0b3fc..bf886e079f6 100644 --- a/test/CodeGen/X86/fast-isel-x86-64.ll +++ b/test/CodeGen/X86/fast-isel-x86-64.ll @@ -119,3 +119,11 @@ define i32 @test10(i32 %X) nounwind { ; CHECK: test10: ; CHECK: shrl $3, } + +define i32 @test11(i32 %X) nounwind { + %Y = sdiv exact i32 %X, 8 + ret i32 %Y +; CHECK: test11: +; CHECK: sarl $3, +} + -- 2.34.1