From f0a95356d649dc0fb65691c4acebee450f3529b4 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 12 Jan 2012 18:27:52 +0000 Subject: [PATCH] Allow targets to select source order pre-RA scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148033 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetLowering.h | 1 + lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 456966b5de1..5c891e940ed 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -56,6 +56,7 @@ namespace llvm { namespace Sched { enum Preference { None, // No preference + Source, // Follow source order. RegPressure, // Scheduling for lowest register pressure. Hybrid, // Scheduling for both latency and register pressure. ILP // Scheduling for ILP in low register pressure mode. diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index bfb6dfa0b17..9f3969959b6 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -218,7 +218,8 @@ namespace llvm { CodeGenOpt::Level OptLevel) { const TargetLowering &TLI = IS->getTargetLowering(); - if (OptLevel == CodeGenOpt::None) + if (OptLevel == CodeGenOpt::None || + TLI.getSchedulingPreference() == Sched::Source) return createSourceListDAGScheduler(IS, OptLevel); if (TLI.getSchedulingPreference() == Sched::RegPressure) return createBURRListDAGScheduler(IS, OptLevel); -- 2.34.1