From f0e3a9c174138ed77f0e5280b5fa735e9b6d5202 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Thu, 11 Jun 2015 15:34:59 +0000 Subject: [PATCH] Replace string GNU Triples with llvm::Triple in computeDataLayout(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rengolin Reviewed By: rengolin Subscribers: llvm-commits, jfb, rengolin Differential Revision: http://reviews.llvm.org/D10361 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239538 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64TargetMachine.cpp | 9 ++++----- lib/Target/ARM/ARMTargetMachine.cpp | 14 +++++++------- lib/Target/Mips/MipsTargetMachine.cpp | 10 +++++----- lib/Target/R600/AMDGPUTargetMachine.cpp | 9 ++++----- lib/Target/SystemZ/SystemZTargetMachine.cpp | 9 ++++----- 5 files changed, 24 insertions(+), 27 deletions(-) diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index 2b5625dc09e..f0ee6649676 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -115,9 +115,8 @@ static std::unique_ptr createTLOF(const Triple &TT) { } // Helper function to build a DataLayout string -static std::string computeDataLayout(StringRef TT, bool LittleEndian) { - Triple Triple(TT); - if (Triple.isOSBinFormatMachO()) +static std::string computeDataLayout(const Triple &TT, bool LittleEndian) { + if (TT.isOSBinFormatMachO()) return "e-m:o-i64:64-i128:128-n32:64-S128"; if (LittleEndian) return "e-m:e-i64:64-i128:128-n32:64-S128"; @@ -134,8 +133,8 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT, bool LittleEndian) // This nested ternary is horrible, but DL needs to be properly // initialized before TLInfo is constructed. - : LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS, - Options, RM, CM, OL), + : LLVMTargetMachine(T, computeDataLayout(Triple(TT), LittleEndian), TT, CPU, + FS, Options, RM, CM, OL), TLOF(createTLOF(Triple(getTargetTriple()))), isLittle(LittleEndian) { initAsmInfo(); diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 04d2b533c24..a6b56ad7cc6 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -115,11 +115,10 @@ computeTargetABI(const Triple &TT, StringRef CPU, return TargetABI; } -static std::string computeDataLayout(StringRef TT, StringRef CPU, +static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle) { - const Triple Triple(TT); - auto ABI = computeTargetABI(Triple, CPU, Options); + auto ABI = computeTargetABI(TT, CPU, Options); std::string Ret = ""; if (isLittle) @@ -129,7 +128,7 @@ static std::string computeDataLayout(StringRef TT, StringRef CPU, // Big endian. Ret += "E"; - Ret += DataLayout::getManglingComponent(Triple); + Ret += DataLayout::getManglingComponent(TT); // Pointers are 32 bits and aligned to 32 bits. Ret += "-p:32:32"; @@ -159,7 +158,7 @@ static std::string computeDataLayout(StringRef TT, StringRef CPU, // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit // aligned everywhere else. - if (Triple.isOSNaCl()) + if (TT.isOSNaCl()) Ret += "-S128"; else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS) Ret += "-S64"; @@ -176,8 +175,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, - CPU, FS, Options, RM, CM, OL), + : LLVMTargetMachine(T, + computeDataLayout(Triple(TT), CPU, Options, isLittle), + TT, CPU, FS, Options, RM, CM, OL), TargetABI(computeTargetABI(Triple(TT), CPU, Options)), TLOF(createTLOF(Triple(getTargetTriple()))), Subtarget(Triple(TT), CPU, FS, *this, isLittle), isLittle(isLittle) { diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index aed15a05bc2..7d003f5aaba 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -44,12 +44,11 @@ extern "C" void LLVMInitializeMipsTarget() { RegisterTargetMachine B(TheMips64elTarget); } -static std::string computeDataLayout(StringRef TT, StringRef CPU, +static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle) { std::string Ret = ""; - MipsABIInfo ABI = - MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions); + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); // There are both little and big endian mips. if (isLittle) @@ -88,8 +87,9 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, - CPU, FS, Options, RM, CM, OL), + : LLVMTargetMachine(T, + computeDataLayout(Triple(TT), CPU, Options, isLittle), + TT, CPU, FS, Options, RM, CM, OL), isLittle(isLittle), TLOF(make_unique()), ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)), Subtarget(nullptr), diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index 0e37127725c..bb5d9e99ff4 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -51,11 +51,10 @@ static MachineSchedRegistry SchedCustomRegistry("r600", "Run R600's custom scheduler", createR600MachineScheduler); -static std::string computeDataLayout(StringRef TT) { - Triple Triple(TT); +static std::string computeDataLayout(const Triple &TT) { std::string Ret = "e-p:32:32"; - if (Triple.getArch() == Triple::amdgcn) { + if (TT.getArch() == Triple::amdgcn) { // 32-bit private, local, and region pointers. 64-bit global and constant. Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"; } @@ -71,8 +70,8 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM, - OptLevel), + : LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options, + RM, CM, OptLevel), TLOF(new TargetLoweringObjectFileELF()), Subtarget(Triple(TT), CPU, FS, *this), IntrinsicInfo() { setRequiresStructuredCFG(true); diff --git a/lib/Target/SystemZ/SystemZTargetMachine.cpp b/lib/Target/SystemZ/SystemZTargetMachine.cpp index 8de050a3b0d..f9de157b8f2 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -43,9 +43,8 @@ static bool UsesVectorABI(StringRef CPU, StringRef FS) { return VectorABI; } -static std::string computeDataLayout(StringRef TT, StringRef CPU, +static std::string computeDataLayout(const Triple &TT, StringRef CPU, StringRef FS) { - const Triple Triple(TT); bool VectorABI = UsesVectorABI(CPU, FS); std::string Ret = ""; @@ -53,7 +52,7 @@ static std::string computeDataLayout(StringRef TT, StringRef CPU, Ret += "E"; // Data mangling. - Ret += DataLayout::getManglingComponent(Triple); + Ret += DataLayout::getManglingComponent(TT); // Make sure that global data has at least 16 bits of alignment by // default, so that we can refer to it using LARL. We don't have any @@ -84,8 +83,8 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, - RM, CM, OL), + : LLVMTargetMachine(T, computeDataLayout(Triple(TT), CPU, FS), TT, CPU, FS, + Options, RM, CM, OL), TLOF(make_unique()), Subtarget(Triple(TT), CPU, FS, *this) { initAsmInfo(); -- 2.34.1