From f179b3f1d91581c29421225d089cd85d28e14d2e Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Fri, 20 Feb 2015 08:24:37 +0000 Subject: [PATCH] Get the cached subtarget off the MachineFunction rather than inquiring for a new one from the TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229999 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMFrameLowering.cpp | 2 +- lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 +- lib/Target/ARM/ARMInstrInfo.cpp | 2 +- lib/Target/ARM/ARMMachineFunctionInfo.cpp | 4 ++-- lib/Target/ARM/ARMRegisterInfo.td | 10 +++++----- lib/Target/ARM/ARMSelectionDAGInfo.cpp | 9 +++++---- lib/Target/ARM/MLxExpansionPass.cpp | 2 +- lib/Target/ARM/Thumb1InstrInfo.cpp | 2 +- 8 files changed, 17 insertions(+), 16 deletions(-) diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp index 62e17ad89f7..5a5bd574aca 100644 --- a/lib/Target/ARM/ARMFrameLowering.cpp +++ b/lib/Target/ARM/ARMFrameLowering.cpp @@ -1864,7 +1864,7 @@ static const uint64_t kSplitStackAvailable = 256; void ARMFrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const { unsigned Opcode; unsigned CFIIndex; - const ARMSubtarget *ST = &MF.getTarget().getSubtarget(); + const ARMSubtarget *ST = &MF.getSubtarget(); bool Thumb = ST->isThumb(); // Sadly, this currently doesn't support varargs, platforms other than diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 6410b338238..77464bd47ea 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -70,7 +70,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. - Subtarget = &MF.getTarget().getSubtarget(); + Subtarget = &MF.getSubtarget(); SelectionDAGISel::runOnMachineFunction(MF); return true; } diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 9ef2204a87f..bc617f08743 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -93,7 +93,7 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI, Reloc::Model RM) const { MachineFunction &MF = *MI->getParent()->getParent(); - const ARMSubtarget &Subtarget = MF.getTarget().getSubtarget(); + const ARMSubtarget &Subtarget = MF.getSubtarget(); if (!Subtarget.useMovt(MF)) { if (RM == Reloc::PIC_) diff --git a/lib/Target/ARM/ARMMachineFunctionInfo.cpp b/lib/Target/ARM/ARMMachineFunctionInfo.cpp index 892b269fc18..229d04165ed 100644 --- a/lib/Target/ARM/ARMMachineFunctionInfo.cpp +++ b/lib/Target/ARM/ARMMachineFunctionInfo.cpp @@ -14,8 +14,8 @@ using namespace llvm; void ARMFunctionInfo::anchor() { } ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF) - : isThumb(MF.getTarget().getSubtarget().isThumb()), - hasThumb2(MF.getTarget().getSubtarget().hasThumb2()), + : isThumb(MF.getSubtarget().isThumb()), + hasThumb2(MF.getSubtarget().hasThumb2()), StByValParamsPadding(0), ArgRegsSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false), LRSpilledForFarJump(false), FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index b290e7f6679..45cc9ea91f3 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -199,7 +199,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), // Thumb1 instructions that know how to use hi regs. let AltOrders = [(add LR, GPR), (trunc GPR, 8)]; let AltOrderSelect = [{ - return 1 + MF.getTarget().getSubtarget().isThumb1Only(); + return 1 + MF.getSubtarget().isThumb1Only(); }]; } @@ -209,7 +209,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; let AltOrderSelect = [{ - return 1 + MF.getTarget().getSubtarget().isThumb1Only(); + return 1 + MF.getSubtarget().isThumb1Only(); }]; } @@ -219,7 +219,7 @@ def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> { let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; let AltOrderSelect = [{ - return 1 + MF.getTarget().getSubtarget().isThumb1Only(); + return 1 + MF.getSubtarget().isThumb1Only(); }]; } @@ -237,7 +237,7 @@ def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>; def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)]; let AltOrderSelect = [{ - return 1 + MF.getTarget().getSubtarget().isThumb1Only(); + return 1 + MF.getSubtarget().isThumb1Only(); }]; } @@ -255,7 +255,7 @@ def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>; def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> { let AltOrders = [(and tcGPR, tGPR)]; let AltOrderSelect = [{ - return MF.getTarget().getSubtarget().isThumb1Only(); + return MF.getSubtarget().isThumb1Only(); }]; } diff --git a/lib/Target/ARM/ARMSelectionDAGInfo.cpp b/lib/Target/ARM/ARMSelectionDAGInfo.cpp index fa30ac31a30..636205fc9e3 100644 --- a/lib/Target/ARM/ARMSelectionDAGInfo.cpp +++ b/lib/Target/ARM/ARMSelectionDAGInfo.cpp @@ -32,7 +32,8 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { - const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget(); + const ARMSubtarget &Subtarget = + DAG.getMachineFunction().getSubtarget(); // Do repeated 4-byte loads and stores. To be improved. // This requires 4-byte alignment. if ((Align & 3) != 0) @@ -150,14 +151,14 @@ EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const { - const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget(); + const ARMSubtarget &Subtarget = + DAG.getMachineFunction().getSubtarget(); // Use default for non-AAPCS (or MachO) subtargets if (!Subtarget.isAAPCS_ABI() || Subtarget.isTargetMachO() || Subtarget.isTargetWindows()) return SDValue(); - const ARMTargetLowering &TLI = - *DAG.getTarget().getSubtarget().getTargetLowering(); + const ARMTargetLowering &TLI = *Subtarget.getTargetLowering(); TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; diff --git a/lib/Target/ARM/MLxExpansionPass.cpp b/lib/Target/ARM/MLxExpansionPass.cpp index 35fe9b3342d..51e519d6d3b 100644 --- a/lib/Target/ARM/MLxExpansionPass.cpp +++ b/lib/Target/ARM/MLxExpansionPass.cpp @@ -381,7 +381,7 @@ bool MLxExpansion::runOnMachineFunction(MachineFunction &Fn) { TII = static_cast(Fn.getSubtarget().getInstrInfo()); TRI = Fn.getSubtarget().getRegisterInfo(); MRI = &Fn.getRegInfo(); - const ARMSubtarget *STI = &Fn.getTarget().getSubtarget(); + const ARMSubtarget *STI = &Fn.getSubtarget(); isLikeA9 = STI->isLikeA9() || STI->isSwift(); isSwift = STI->isSwift(); diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp index 8ea912e2703..c24f740043e 100644 --- a/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -44,7 +44,7 @@ void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, bool KillSrc) const { // Need to check the arch. MachineFunction &MF = *MBB.getParent(); - const ARMSubtarget &st = MF.getTarget().getSubtarget(); + const ARMSubtarget &st = MF.getSubtarget(); assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && "Thumb1 can only copy GPR registers"); -- 2.34.1