From f2217176e04f8a3572c41f93c819f3d25713d5f0 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 21 Feb 2017 11:14:05 +0800 Subject: [PATCH] ASoC: rockchip: i2s: add a delay before i2s clear in order to keep i2s lrck signal integrity, when i2s stop, need at least one lrck cycle to ensure signal integrity. the max delay time is when lrck is 8khz, the delay time is 125us(1/8khz), using udelay(150) with a 25us margin. Change-Id: Ia0b0c8b0153e25ed3686eee2e13f370d0c3da380 Signed-off-by: Sugar Zhang --- sound/soc/rockchip/rockchip_i2s.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 711c3db889cb..68fea0a32eee 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -117,6 +117,7 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); + udelay(150); regmap_update_bits(i2s->regmap, I2S_CLR, I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_TXC | I2S_CLR_RXC); @@ -163,6 +164,7 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); + udelay(150); regmap_update_bits(i2s->regmap, I2S_CLR, I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_TXC | I2S_CLR_RXC); -- 2.34.1