From f4fc36e738a208921d6debecb258d6acd2e3b628 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 19 Jul 2004 07:52:35 +0000 Subject: [PATCH] Inline 4 methods git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15000 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SparcV9/SparcV9CodeEmitter.cpp | 8 +++---- lib/Target/SparcV9/SparcV9InstrInfo.cpp | 24 +++++++++---------- .../SparcV9/SparcV9PrologEpilogInserter.cpp | 4 ++-- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp index 4f4f0b3b915..271dcf1c6b4 100644 --- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp +++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp @@ -757,10 +757,10 @@ bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) { if (op.isHiBits64()) { hiBits64=true; } MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed, branchTarget); - if (loBits32) { MI->setOperandLo32(ii); } - else if (hiBits32) { MI->setOperandHi32(ii); } - else if (loBits64) { MI->setOperandLo64(ii); } - else if (hiBits64) { MI->setOperandHi64(ii); } + if (loBits32) { MI->getOperand(ii).markLo32(); } + else if (hiBits32) { MI->getOperand(ii).markHi32(); } + else if (loBits64) { MI->getOperand(ii).markLo64(); } + else if (hiBits64) { MI->getOperand(ii).markHi64(); } DEBUG(std::cerr << "Rewrote BB ref: "); unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI); MCE.emitWordAt (fixedInstr, Ref); diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp index 30d35546e6c..f672b5dc6d5 100644 --- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp +++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp @@ -164,7 +164,7 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C, // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) { miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest); - miSETHI->setOperandHi32(0); + miSETHI->getOperand(0).markHi32(); mvec.push_back(miSETHI); } @@ -174,7 +174,7 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C, if (miSETHI) { // unsigned value with high-order bits set using SETHI miOR = BuildMI(V9::ORi,3).addReg(dest).addZImm(C).addRegDef(dest); - miOR->setOperandLo32(1); + miOR->getOperand(1).markLo32(); } else { // unsigned or small signed value that fits in simm13 field of OR assert(smallNegValue || (C & ~MAXSIMM) == 0); @@ -261,12 +261,12 @@ CreateSETUWLabel(const TargetMachine& target, Value* val, // Set the high 22 bits in dest MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(dest); - MI->setOperandHi32(0); + MI->getOperand(0).markHi32(); mvec.push_back(MI); // Set the low 10 bits in dest MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(val).addRegDef(dest); - MI->setOperandLo32(1); + MI->getOperand(1).markLo32(); mvec.push_back(MI); } @@ -288,24 +288,24 @@ CreateSETXLabel(const TargetMachine& target, MachineInstr* MI; MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg); - MI->setOperandHi64(0); + MI->getOperand(0).markHi64(); mvec.push_back(MI); MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg); - MI->setOperandLo64(1); + MI->getOperand(1).markLo64(); mvec.push_back(MI); mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32) .addRegDef(tmpReg)); MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(dest); - MI->setOperandHi32(0); + MI->getOperand(0).markHi32(); mvec.push_back(MI); MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(tmpReg).addRegDef(dest); mvec.push_back(MI); MI = BuildMI(V9::ORi, 3).addReg(dest).addPCDisp(val).addRegDef(dest); - MI->setOperandLo32(1); + MI->getOperand(1).markLo32(); mvec.push_back(MI); } @@ -512,18 +512,18 @@ SparcV9InstrInfo::CreateCodeToLoadConst(const TargetMachine& target, MachineInstr* MI; MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(tmpReg); - MI->setOperandHi64(0); + MI->getOperand(0).markHi64(); mvec.push_back(MI); MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addConstantPoolIndex(CPI) .addRegDef(tmpReg); - MI->setOperandLo64(1); + MI->getOperand(1).markLo64(); mvec.push_back(MI); mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32) .addRegDef(tmpReg)); MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(addrReg); - MI->setOperandHi32(0); + MI->getOperand(0).markHi32(); mvec.push_back(MI); MI = BuildMI(V9::ORr, 3).addReg(addrReg).addReg(tmpReg).addRegDef(addrReg); @@ -531,7 +531,7 @@ SparcV9InstrInfo::CreateCodeToLoadConst(const TargetMachine& target, MI = BuildMI(V9::ORi, 3).addReg(addrReg).addConstantPoolIndex(CPI) .addRegDef(addrReg); - MI->setOperandLo32(1); + MI->getOperand(1).markLo32(); mvec.push_back(MI); // Now load the constant from out ConstantPool label diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp index d6b34b65959..d852dee1ed3 100644 --- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp +++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp @@ -93,12 +93,12 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF) MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C) .addMReg(uregNum, MachineOperand::Def); - M->setOperandHi32(0); + M->getOperand(0).markHi32(); mvec.push_back(M); M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C) .addMReg(uregNum, MachineOperand::Def); - M->setOperandLo32(1); + M->getOperand(1).markLo32(); mvec.push_back(M); M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0) -- 2.34.1