From f53288c80ca1e06a4a9b3de5e3e88f4c5b4efd6e Mon Sep 17 00:00:00 2001 From: xjh Date: Tue, 13 May 2014 19:53:08 +0800 Subject: [PATCH] MIPI: support uboot logo on --- arch/arm/boot/dts/lcd-wqxga-mipi.dtsi | 30 +- drivers/video/rockchip/screen/lcd_mipi.c | 227 ++++++++++++- drivers/video/rockchip/transmitter/mipi_dsi.c | 63 +++- drivers/video/rockchip/transmitter/mipi_dsi.h | 4 + .../rockchip/transmitter/rk32_mipi_dsi.c | 319 ++++++++++++++++-- .../rockchip/transmitter/rk32_mipi_dsi.h | 10 +- 6 files changed, 602 insertions(+), 51 deletions(-) diff --git a/arch/arm/boot/dts/lcd-wqxga-mipi.dtsi b/arch/arm/boot/dts/lcd-wqxga-mipi.dtsi index 71e46a7c72f5..de22c304a655 100755 --- a/arch/arm/boot/dts/lcd-wqxga-mipi.dtsi +++ b/arch/arm/boot/dts/lcd-wqxga-mipi.dtsi @@ -11,24 +11,30 @@ / { /* about mipi */ disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; rockchip,screen_init = <1>; rockchip,dsi_lane = <4>; - rockchip,dsi_hs_clk = <950>; + rockchip,dsi_hs_clk = <970>; rockchip,mipi_dsi_num = <2>; }; disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; rockchip,gpios = <&gpio7 GPIO_B2 GPIO_ACTIVE_HIGH>; - rockchip,delay = <100>; + rockchip,delay = <20>; }; /*mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; rockchip,gpios = <&gpio6 GPIO_A7 GPIO_ACTIVE_HIGH>; rockchip,delay = <10>; };*/ }; disp_mipi_init_cmds: screen-on-cmds { rockchip,cmd_debug = <0>; + compatible = "rockchip,screen-on-cmds"; rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x05 0x01>; //set soft reset @@ -36,54 +42,63 @@ }; rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x15 0x3a 0x77>; rockchip,cmd_delay = <0>; }; rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x39 0x2a 0x00 0x00 0x04 0xff>; rockchip,cmd_delay = <0>; }; rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x39 0x2b 0x00 0x00 0x06 0x3f>; rockchip,cmd_delay = <0>; }; rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <1>; rockchip,cmd = <0x15 0x35 0x00>; rockchip,cmd_delay = <0>; }; rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <1>; rockchip,cmd = <0x39 0x44 0x00 0x00>; rockchip,cmd_delay = <0>; }; rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x15 0x51 0xff>; //0xff rockchip,cmd_delay = <0>; }; rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x15 0x53 0x24>; rockchip,cmd_delay = <0>; }; rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x15 0x51 0xff>; //0xff rockchip,cmd_delay = <0>; }; rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x15 0x53 0x24>; @@ -91,12 +106,14 @@ }; rockchip,on-cmds11 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x15 0x55 0x03>; rockchip,cmd_delay = <0>; }; rockchip,on-cmds12 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x05 dcs_exit_sleep_mode>; @@ -104,6 +121,7 @@ }; rockchip,on-cmds13 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x23 0xb0 0x00>; @@ -111,6 +129,7 @@ }; rockchip,on-cmds14 { //video + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x29 0xb3 0x1c>; @@ -118,18 +137,21 @@ }; rockchip,on-cmds15 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x29 0xce 0x7d 0x40 0x48 0x56 0x67 0x78 0x88 0x98 0xa7 0xb5 0xc3 0xd1 0xde 0xe9 0xf2 0xfa 0xff 0x04 0x00>; rockchip,cmd_delay = <0>; }; rockchip,on-cmds16 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x23 0xb0 0x03>; rockchip,cmd_delay = <0>; }; rockchip,on-cmds17 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x39 0x2c >; @@ -137,6 +159,7 @@ }; rockchip,on-cmds18 { + compatible = "rockchip,on-cmds"; rockchip,cmd_type = ; rockchip,dsi_id = <2>; rockchip,cmd = <0x05 dcs_set_display_on>; @@ -147,11 +170,12 @@ disp_timings: display-timings { native-mode = <&timing0>; + compatible = "rockchip,display-timings"; timing0: timing0 { screen-type = ; lvds-format = ; out-face = ; - clock-frequency = <280000000>; + clock-frequency = <285000000>; hactive = <2560>; vactive = <1600>; diff --git a/drivers/video/rockchip/screen/lcd_mipi.c b/drivers/video/rockchip/screen/lcd_mipi.c index 9689f5af9d02..230fbefc3cad 100755 --- a/drivers/video/rockchip/screen/lcd_mipi.c +++ b/drivers/video/rockchip/screen/lcd_mipi.c @@ -13,15 +13,39 @@ * GNU General Public License for more details. */ +#ifndef CONFIG_LCD_MIPI +#include +#endif +#ifdef CONFIG_LCD_MIPI #include "../transmitter/mipi_dsi.h" #include +#endif +#ifdef CONFIG_RK_3288_DSI_UBOOT +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../transmitter/mipi_dsi.h" +#endif -#if 0 +#ifdef CONFIG_RK_3288_DSI_UBOOT +#define MIPI_SCREEN_DBG(x...) //printf(x) +#elif defined CONFIG_LCD_MIPI #define MIPI_SCREEN_DBG(x...) printk(KERN_ERR x) #else #define MIPI_SCREEN_DBG(x...) #endif - +#ifdef CONFIG_RK_3288_DSI_UBOOT +#define msleep(a) udelay(a * 1000) +#define printk(x...) //printf(x) +#endif static struct mipi_screen *gmipi_screen; static void rk_mipi_screen_pwr_disable(struct mipi_screen *screen) @@ -251,7 +275,7 @@ int rk_mipi_screen_standby(u8 enable) } return 0; } - +#ifdef CONFIG_LCD_MIPI static int rk_mipi_screen_init_dt(struct mipi_screen *screen) { struct device_node *childnode, *grandchildnode, *root; @@ -489,26 +513,216 @@ static int rk_mipi_screen_init_dt(struct mipi_screen *screen) } return 0; } - +#endif int rk_mipi_get_dsi_num(void) { return gmipi_screen->mipi_dsi_num; } +#ifdef CONFIG_LCD_MIPI EXPORT_SYMBOL(rk_mipi_get_dsi_num); - +#endif int rk_mipi_get_dsi_lane(void) { return gmipi_screen->dsi_lane; } +#ifdef CONFIG_LCD_MIPI EXPORT_SYMBOL(rk_mipi_get_dsi_lane); - +#endif int rk_mipi_get_dsi_clk(void) { return gmipi_screen->hs_tx_clk; } +#ifdef CONFIG_LCD_MIPI EXPORT_SYMBOL(rk_mipi_get_dsi_clk); +#endif +#ifdef CONFIG_RK_3288_DSI_UBOOT +static int rk_mipi_screen_init_dt(struct mipi_screen *screen) +{ + struct mipi_dcs_cmd_ctr_list *dcs_cmd; + u32 i,cmds[20],length; + int err; + int node; + void *blob; + struct fdt_gpio_state gpio_val; + int noffset; + + INIT_LIST_HEAD(&screen->cmdlist_head); + + blob = getenv_hex("fdtaddr", 0); + node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_INIT); + if(node < 0){ + MIPI_SCREEN_DBG("Can not get node of COMPAT_ROCKCHIP_MIPI_INIT\n"); + } + screen->screen_init = fdtdec_get_int(blob, node, "rockchip,screen_init", -1); + if(screen->screen_init < 0){ + MIPI_SCREEN_DBG("Can not get screen_init\n"); + } + screen->dsi_lane = fdtdec_get_int(blob, node, "rockchip,dsi_lane", -1); + if(screen->dsi_lane < 0){ + MIPI_SCREEN_DBG("Can not get dsi_lane\n"); + } + screen->hs_tx_clk= fdtdec_get_int(blob, node, "rockchip,dsi_hs_clk", -1); + if(screen->hs_tx_clk < 0){ + MIPI_SCREEN_DBG("Can not get dsi_hs_clk\n"); + }else{ + screen->hs_tx_clk = screen->hs_tx_clk*MHZ; + } + screen->mipi_dsi_num= fdtdec_get_int(blob, node, "rockchip,mipi_dsi_num", -1); + if(screen->mipi_dsi_num < 0){ + MIPI_SCREEN_DBG("Can't get mipi_dsi_num\n"); + } + #if 0 + node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_PWR); + if(node < 0){ + printf("Can not get node of COMPAT_ROCKCHIP_MIPI_PWR\n"); + } + #endif +#if 0 + /*get the lcd rst status*/ +// handle = fdt_getprop_u32_default(blob, "/mipi_power_ctr", "mipi_lcd_rst", -1); +// node = fdt_node_offset_by_phandle(blob, handle); + node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_PWR); + if(node < 0){ + printf("Can not get node of COMPAT_ROCKCHIP_MIPI_PWR\n"); + }else{ + subnode = fdtdec_next_compatible_subnode(blob, node, + COMPAT_ROCKCHIP_MIPI_LCD_RST, &depth); + if (subnode <=0) { + screen->lcd_rst_gpio = INVALID_GPIO; + printf("Can't get pin of mipi_lcd_rst\n"); + } else { + err = fdtdec_decode_gpio(blob, subnode, "rockchip,gpios", &gpio_val); + gpio_val.gpio = rk_gpio_base_to_bank(gpio_val.gpio & RK_GPIO_BANK_MASK) | (gpio_val.gpio & RK_GPIO_PIN_MASK); + if(err < 0){ + screen->lcd_rst_gpio = INVALID_GPIO; + printf("Can't find GPIO rst\n"); + }else{ + screen->lcd_rst_gpio = gpio_val.gpio; + screen->lcd_rst_atv_val = !(gpio_val.flags & OF_GPIO_ACTIVE_LOW); + } + screen->lcd_rst_delay = fdtdec_get_int(blob, subnode, "rockchip,delay", -1); + if(screen->lcd_rst_delay < 0){ + printf("Can't get delay of rst delay\n"); + } + printf("Get lcd rst gpio and delay successfully!\n"); + } + } + #endif + /*get the lcd rst & en status*/ + node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_PWR); + if(node < 0){ + MIPI_SCREEN_DBG("Can not get node of COMPAT_ROCKCHIP_MIPI_PWR\n"); + }else{ + #if 0 + noffset = fdt_first_subnode(blob,node); + const char *name = fdt_get_name(blob, noffset, NULL); + printf("XJH_DEBUG1:%s\n",name); + noffset = fdt_next_subnode(blob,noffset); + const char *name1 = fdt_get_name(blob, noffset, NULL); + printf("XJH_DEBUG2:%s\n",name1); + #endif + for (noffset = fdt_first_subnode(blob,node); + noffset >= 0; + noffset = fdt_next_subnode(blob, noffset)) { + if ( 0 == fdt_node_check_compatible(blob, noffset, "rockchip,lcd_rst")){ + err = fdtdec_decode_gpio(blob, noffset, "rockchip,gpios", &gpio_val); + gpio_val.gpio = rk_gpio_base_to_bank(gpio_val.gpio & RK_GPIO_BANK_MASK) | (gpio_val.gpio & RK_GPIO_PIN_MASK); + if(err < 0){ + screen->lcd_rst_gpio = INVALID_GPIO; + MIPI_SCREEN_DBG("Can't find GPIO rst\n"); + }else{ + screen->lcd_rst_gpio = gpio_val.gpio; + screen->lcd_rst_atv_val = !(gpio_val.flags & OF_GPIO_ACTIVE_LOW); + } + screen->lcd_rst_delay = fdtdec_get_int(blob, noffset, "rockchip,delay", -1); + if(screen->lcd_rst_delay < 0){ + MIPI_SCREEN_DBG("Can't get delay of rst delay\n"); + } + MIPI_SCREEN_DBG("Get lcd rst gpio and delay successfully!\n"); + } + if ( 0 == fdt_node_check_compatible(blob, noffset, "rockchip,lcd_en")){ + + err = fdtdec_decode_gpio(blob, noffset, "rockchip,gpios", &gpio_val); + gpio_val.gpio = rk_gpio_base_to_bank(gpio_val.gpio & RK_GPIO_BANK_MASK) | (gpio_val.gpio & RK_GPIO_PIN_MASK); + if(err < 0){ + screen->lcd_en_gpio = INVALID_GPIO; + MIPI_SCREEN_DBG("Can't find GPIO en\n"); + }else{ + screen->lcd_en_gpio = gpio_val.gpio; + screen->lcd_en_atv_val = !(gpio_val.flags & OF_GPIO_ACTIVE_LOW); + } + screen->lcd_en_delay = fdtdec_get_int(blob, noffset, "rockchip,delay", -1); + if(screen->lcd_en_delay < 0){ + MIPI_SCREEN_DBG("Can't get delay of lcd_en delay\n"); + } + MIPI_SCREEN_DBG("Get lcd en gpio and delay successfully:delay %d!\n",screen->lcd_en_delay); + } + } + } + + /*get the initial command list*/ + node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_MIPI_SONCMDS); + if(node < 0){ + MIPI_SCREEN_DBG("Can not get node of COMPAT_ROCKCHIP_MIPI_SONCMDS\n"); + }else{ + for (noffset = fdt_first_subnode(blob,node); + noffset >= 0; + noffset = fdt_next_subnode(blob, noffset)) { + + MIPI_SCREEN_DBG("build MIPI LCD init cmd tables\n"); + // subnode = fdtdec_next_compatible_subnode(blob, node, + // COMPAT_ROCKCHIP_MIPI_ONCMDS, &depth); + // if (noffset < 0) + // break; + dcs_cmd = calloc(1,sizeof(struct mipi_dcs_cmd_ctr_list)); + //node = fdt_node_offset_by_phandle(blob, handle); + strcpy(dcs_cmd->dcs_cmd.name, fdt_get_name(blob, noffset, NULL)); + MIPI_SCREEN_DBG("%s\n",dcs_cmd->dcs_cmd.name); + dcs_cmd->dcs_cmd.type = fdtdec_get_int(blob, noffset, "rockchip,cmd_type", -1); + MIPI_SCREEN_DBG("dcs_cmd.type=%02x\n",dcs_cmd->dcs_cmd.type); + dcs_cmd->dcs_cmd.dsi_id = fdtdec_get_int(blob, noffset, "rockchip,dsi_id", -1); + MIPI_SCREEN_DBG("dcs_cmd.dsi_id=%02x\n",dcs_cmd->dcs_cmd.dsi_id); + err = fdt_getprop(blob, noffset, "rockchip,cmd", &length); + dcs_cmd->dcs_cmd.cmd_len = length / sizeof(u32) ; + err = fdtdec_get_int_array(blob, noffset, "rockchip,cmd", cmds, dcs_cmd->dcs_cmd.cmd_len); + MIPI_SCREEN_DBG("length=%d,cmd_len = %d err = %d\n",length,dcs_cmd->dcs_cmd.cmd_len,err); + for(i = 0; i < (length / sizeof(u32)); i++){ + MIPI_SCREEN_DBG("cmd[%d]=0x%08x, ",i+1,cmds[i]); + dcs_cmd->dcs_cmd.cmds[i] = cmds[i]; + } + MIPI_SCREEN_DBG("\n"); + dcs_cmd->dcs_cmd.delay = fdtdec_get_int(blob, noffset, "rockchip,cmd_delay", -1); + MIPI_SCREEN_DBG("dcs_cmd.delay=%d\n",dcs_cmd->dcs_cmd.delay); + list_add_tail(&dcs_cmd->list, &screen->cmdlist_head); + } + } + + return 0; +} + +int rk_mipi_screen_probe(void) +{ + int ret = 0; + gmipi_screen = calloc(1, sizeof(struct mipi_screen)); + if(!gmipi_screen) { + printf("request struct screen fail!\n"); + return -ENOMEM; + } + ret = rk_mipi_screen_init_dt(gmipi_screen); + if(ret < 0){ + printf(" rk_mipi_screen_init_dt fail!\n"); + return -1; + } + +// MIPI_SCREEN_DBG("---rk_mipi_screen_probe--end\n"); + + return 0; +} + +#endif +#ifdef CONFIG_LCD_MIPI static int __init rk_mipi_screen_probe(struct platform_device *pdev) { static int ret = 0; @@ -549,3 +763,4 @@ static void __exit rk_mipi_screen_exit(void) subsys_initcall_sync(rk_mipi_screen_init); module_exit(rk_mipi_screen_exit); +#endif diff --git a/drivers/video/rockchip/transmitter/mipi_dsi.c b/drivers/video/rockchip/transmitter/mipi_dsi.c index 3e910b3788cd..09c4e839bd88 100755 --- a/drivers/video/rockchip/transmitter/mipi_dsi.c +++ b/drivers/video/rockchip/transmitter/mipi_dsi.c @@ -12,8 +12,20 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - - +#ifndef CONFIG_MIPI_DSI +#include +#endif +#ifdef CONFIG_RK_3288_DSI_UBOOT +#include +#include +#include +#include +#include +#include +#include +#include +#include "mipi_dsi.h" +#else #include #include #include @@ -24,6 +36,7 @@ #include #include "mipi_dsi.h" +#endif #define MAX_DSI_CHIPS 5 @@ -36,6 +49,9 @@ *v1.3 : fix send commad's methods */ #define MIPI_DSI_VERSION_AND_TIME "mipi_dsi v1.3 2014-04-17" +#ifdef CONFIG_RK_3288_DSI_UBOOT +#define printk(x...) printf(x) +#endif static struct mipi_dsi_ops *dsi_ops[MAX_DSI_CHIPS] = {NULL}; @@ -50,8 +66,9 @@ int register_dsi_ops(unsigned int id, struct mipi_dsi_ops *ops) { dsi_ops[id] = ops; return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(register_dsi_ops); - +#endif int del_dsi_ops(struct mipi_dsi_ops *ops) { @@ -70,7 +87,9 @@ int del_dsi_ops(struct mipi_dsi_ops *ops) { } return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(del_dsi_ops); +#endif int dsi_probe_current_chip(unsigned int id) { int ret = 0; @@ -94,8 +113,9 @@ int dsi_probe_current_chip(unsigned int id) { return ret; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_probe_current_chip); - +#endif int dsi_power_up(unsigned int id) { struct mipi_dsi_ops *ops = NULL; @@ -111,8 +131,9 @@ int dsi_power_up(unsigned int id) { ops->power_up(ops->dsi); return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_power_up); - +#endif int dsi_power_off(unsigned int id) { @@ -131,8 +152,9 @@ int dsi_power_off(unsigned int id) { return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_power_off); - +#endif int dsi_set_regs(unsigned int id, void *array, u32 n) { struct mipi_dsi_ops *ops = NULL; @@ -150,8 +172,9 @@ int dsi_set_regs(unsigned int id, void *array, u32 n) { return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_set_regs); - +#endif int dsi_init(unsigned int id, u32 n) { struct mipi_dsi_ops *ops = NULL; @@ -169,8 +192,9 @@ int dsi_init(unsigned int id, u32 n) { return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_init); - +#endif int dsi_enable_video_mode(unsigned int id, u32 enable) { struct mipi_dsi_ops *ops = NULL; @@ -189,8 +213,9 @@ int dsi_enable_video_mode(unsigned int id, u32 enable) { return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_enable_video_mode); - +#endif int dsi_enable_command_mode(unsigned int id, u32 enable) { struct mipi_dsi_ops *ops = NULL; @@ -209,8 +234,9 @@ int dsi_enable_command_mode(unsigned int id, u32 enable) { return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_enable_command_mode); - +#endif int dsi_enable_hs_clk(unsigned int id, u32 enable) { struct mipi_dsi_ops *ops = NULL; @@ -229,8 +255,9 @@ int dsi_enable_hs_clk(unsigned int id, u32 enable) { return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_enable_hs_clk); - +#endif int dsi_is_active(unsigned int id) { struct mipi_dsi_ops *ops = NULL; @@ -248,8 +275,9 @@ int dsi_is_active(unsigned int id) { else return -1; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_is_active); - +#endif int dsi_is_enable(unsigned int id, u32 enable){ struct mipi_dsi_ops *ops = NULL; @@ -268,8 +296,9 @@ int dsi_is_enable(unsigned int id, u32 enable){ return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_is_enable); - +#endif int dsi_send_dcs_packet(unsigned int id, unsigned char *packet, u32 n) { struct mipi_dsi_ops *ops = NULL; @@ -287,8 +316,9 @@ int dsi_send_dcs_packet(unsigned int id, unsigned char *packet, u32 n) { ops->dsi_send_dcs_packet(ops->dsi, packet, n); return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_send_dcs_packet); - +#endif int dsi_read_dcs_packet(unsigned int id, unsigned char *packet, u32 n) { @@ -306,8 +336,9 @@ int dsi_read_dcs_packet(unsigned int id, unsigned char *packet, u32 n) { ops->dsi_read_dcs_packet(ops->dsi, packet, n); return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_read_dcs_packet); - +#endif int dsi_send_packet(unsigned int id, unsigned char *packet, u32 n) { @@ -326,4 +357,6 @@ int dsi_send_packet(unsigned int id, unsigned char *packet, u32 n) { return 0; } +#ifdef CONFIG_MIPI_DSI EXPORT_SYMBOL(dsi_send_packet); +#endif diff --git a/drivers/video/rockchip/transmitter/mipi_dsi.h b/drivers/video/rockchip/transmitter/mipi_dsi.h index fc41f3aa5959..7feab832b9d1 100755 --- a/drivers/video/rockchip/transmitter/mipi_dsi.h +++ b/drivers/video/rockchip/transmitter/mipi_dsi.h @@ -14,6 +14,10 @@ drivers/video/rockchip/transmitter/mipi_dsi.h #include #include #endif +#ifdef CONFIG_RK_3288_DSI_UBOOT +#include +#endif + //DSI DATA TYPE #define DTYPE_DCS_SWRITE_0P 0x05 diff --git a/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c b/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c index 14ef6b787a4e..73d4a9221125 100755 --- a/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c +++ b/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c @@ -15,10 +15,31 @@ */ //config +#ifndef CONFIG_RK32_MIPI_DSI +#include +#endif + +#ifdef CONFIG_RK32_MIPI_DSI #define MIPI_DSI_REGISTER_IO 0 #define CONFIG_MIPI_DSI_LINUX 0 +#endif #define DWC_DSI_VERSION 0x3133302A +#ifdef CONFIG_RK_3288_DSI_UBOOT +#include +#include +#include +#include +#include +#include +#include "mipi_dsi.h" +#include "rk32_mipi_dsi.h" +#include "mipi_dsi.h" +#include +#include +#include +#include +#else #include #include #include @@ -39,9 +60,12 @@ #include "mipi_dsi.h" #include "rk32_mipi_dsi.h" #include - -#if 0 +#endif +#ifdef CONFIG_RK32_MIPI_DSI #define MIPI_DBG(x...) printk(KERN_INFO x) +#elif defined CONFIG_RK_3288_DSI_UBOOT +#define MIPI_DBG(x...) //printf( x) +#define printk(x...) //printf( x) #else #define MIPI_DBG(x...) #endif @@ -66,7 +90,7 @@ * */ -#define RK_MIPI_DSI_VERSION_AND_TIME "rockchip mipi_dsi v1.0 2014-05-07" +#define RK_MIPI_DSI_VERSION_AND_TIME "rockchip mipi_dsi v1.0 2014-05-08" static struct dsi *dsi0; static struct dsi *dsi1; @@ -78,6 +102,42 @@ static int rk32_mipi_dsi_enable_command_mode(void *arg, u32 enable); static int rk32_mipi_dsi_is_enable(void *arg, u32 enable); int rk_mipi_screen_standby(u8 enable); +#ifdef CONFIG_RK_3288_DSI_UBOOT +#define msleep(a) udelay(a * 1000) +/* +dsihost0: +clocks = <&clk_gates5 15>, <&clk_gates16 4>; +clock-names = "clk_mipi_24m", "pclk_mipi_dsi"; + +dsihost1: +clocks = <&clk_gates5 15>, <&clk_gates16 5>; +clock-names = "clk_mipi_24m", "pclk_mipi_dsi"; + +*/ +int rk32_mipi_dsi_clk_enable(struct dsi *dsi) +{ + u32 val; + val = 0x80000000;//bit31~bit16 + writel(val, RK3288_CRU_PHYS + 0x174); /*24M*/ + if(dsi->dsi_id == 0) + val = (1 << 20); + else + val = (1 << 21); + writel(val, RK3288_CRU_PHYS + 0x1a0); /*pclk*/ +} +int rk32_mipi_dsi_clk_disable(struct dsi *dsi) +{ + u32 val; + if(dsi->dsi_id == 0) + val = (1 << 20)|(1 << 4); + else + val = (1 << 21)|(1 << 5); + writel(val, RK3288_CRU_PHYS + 0x1a0); /*pclk*/ + + val = 0x80008000;//bit31~bit16 + writel(val, RK3288_CRU_PHYS + 0x174); /*24M*/} + +#endif static int rk32_dsi_read_reg(struct dsi *dsi, u16 reg, u32 *pval) { *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET)); @@ -173,19 +233,26 @@ static int rk32_dwc_phy_test_wr(struct dsi *dsi, unsigned char test_code, unsign static int rk32_phy_power_up(struct dsi *dsi) { - //enable ref clock - clk_prepare_enable(dsi->phy.refclk); - clk_prepare_enable(dsi->dsi_pclk); - clk_prepare_enable(dsi->dsi_pd); - udelay(10); + //enable ref clock + #ifdef CONFIG_RK_3288_DSI_UBOOT + rk32_mipi_dsi_clk_enable(dsi); + #else + clk_prepare_enable(dsi->phy.refclk); + clk_prepare_enable(dsi->dsi_pclk); + clk_prepare_enable(dsi->dsi_pd); + #endif + udelay(10); switch(dsi->host.lane) { case 4: rk32_dsi_set_bits(dsi, 3, n_lanes); + break; case 3: rk32_dsi_set_bits(dsi, 2, n_lanes); + break; case 2: rk32_dsi_set_bits(dsi, 1, n_lanes); + break; case 1: rk32_dsi_set_bits(dsi, 0, n_lanes); break; @@ -202,12 +269,15 @@ static int rk32_phy_power_up(struct dsi *dsi) static int rk32_phy_power_down(struct dsi *dsi) { - rk32_dsi_set_bits(dsi, 0, phy_shutdownz); - clk_disable_unprepare(dsi->phy.refclk); - clk_disable_unprepare(dsi->dsi_pclk); - clk_disable_unprepare(dsi->dsi_pd); - - return 0; + rk32_dsi_set_bits(dsi, 0, phy_shutdownz); + #ifdef CONFIG_RK_3288_DSI_UBOOT + rk32_mipi_dsi_clk_disable(dsi); + #else + clk_disable_unprepare(dsi->phy.refclk); + clk_disable_unprepare(dsi->dsi_pclk); + clk_disable_unprepare(dsi->dsi_pd); + #endif + return 0; } static int rk32_phy_init(struct dsi *dsi) @@ -560,13 +630,16 @@ static int rk_mipi_dsi_init(void *arg, u32 n) if(((screen->type == SCREEN_DUAL_MIPI) && (rk_mipi_get_dsi_num() == 1)) || ((screen->type == SCREEN_MIPI) && (rk_mipi_get_dsi_num() == 2))){ MIPI_TRACE("dsi number and mipi type not match!\n"); return -1; - } - + } +#ifdef CONFIG_RK_3288_DSI_UBOOT + dsi->phy.Tpclk = div_u64(1000000000000llu, screen->pixclock); + dsi->phy.ref_clk = 24*MHZ; +#else dsi->phy.Tpclk = rk_fb_get_prmry_screen_pixclock(); if(dsi->phy.refclk) dsi->phy.ref_clk = clk_get_rate(dsi->phy.refclk) ; - +#endif dsi->phy.sys_clk = dsi->phy.ref_clk; printk("dsi->phy.sys_clk =%d\n",dsi->phy.sys_clk ); @@ -1194,12 +1267,49 @@ struct file_operations reg_proc_fops1 = { .read = reg_proc_read1, }; #endif - +#ifdef CONFIG_MIPI_DSI_LINUX static irqreturn_t rk32_mipi_dsi_irq_handler(int irq, void *data) { printk("-------rk32_mipi_dsi_irq_handler-------\n"); return IRQ_HANDLED; } +#endif +#ifdef CONFIG_RK_3288_DSI_UBOOT +int rk32_dsi_sync(void) +{ + /* + After the core reset, DPI waits for the first VSYNC active transition to start signal sampling, including + pixel data, and preventing image transmission in the middle of a frame. + */ + dsi_is_enable(0, 0); + if (rk_mipi_get_dsi_num() ==2) + dsi_is_enable(1, 0); + + dsi_enable_video_mode(0, 1); + dsi_enable_video_mode(1, 1); + + dsi_is_enable(0, 1); + if (rk_mipi_get_dsi_num() ==2) + dsi_is_enable(1, 1); +} + +#endif +static int dwc_phy_test_rd(struct dsi *dsi, unsigned char test_code) +{ + int val = 0; + + + + + rk32_dsi_set_bits(dsi, 0x10000 | test_code, PHY_TEST_CTRL1); + rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0); + rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0); + + val = rk32_dsi_get_bits(dsi, PHY_TEST_CTRL1); + + + return val; +} static int rk32_dsi_enable(void) { @@ -1240,12 +1350,13 @@ static int rk32_dsi_disable(void) return 0; } +#ifdef CONFIG_MIPI_DSI_LINUX static struct rk_fb_trsm_ops trsm_dsi_ops = { .enable = rk32_dsi_enable, .disable = rk32_dsi_disable, }; - +#endif static void rk32_init_phy_mode(int lcdc_id) { int val0 = 0, val1 = 0; @@ -1276,17 +1387,176 @@ static void rk32_init_phy_mode(int lcdc_id) writel_relaxed(val1, RK_GRF_VIRT + RK3288_GRF_SOC_CON14); } } +#ifdef CONFIG_RK_3288_DSI_UBOOT +int rk_dsi_host_parse_dt(const void *blob, struct dsi *dsi) +{ + int node; + void *handle; + int length; + + node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_DSIHOST); + do{ + if(fdtdec_get_int(blob, node, "rockchip,prop", -1) != dsi->dsi_id){ + node = fdtdec_next_compatible(blob, node, COMPAT_ROCKCHIP_DSIHOST); + }else{ + break; + } + }while(1); + + //fdtdec_get_addr_size(blob,node,"reg",&length); + dsi->host.membase = fdtdec_get_int(blob, node, "reg", -1); + //fdt_getprop(blob, node, "reg", &length); + MIPI_DBG("dsi->host.membase 0x%08x, length %d\n",dsi->host.membase,length); + return 0; +} + +int rk32_mipi_enable(vidinfo_t *vid) +{ + int ret = 0; + struct dsi *dsi; + struct mipi_dsi_ops *ops; + struct rk_screen *screen; + struct mipi_dsi_screen *dsi_screen; + static int id = 0; + + rk_mipi_screen_probe(); + + do{ + dsi = calloc(1, sizeof(struct dsi)); + if(!dsi) { + MIPI_DBG("request struct dsi.%d fail!\n",id); + return -ENOMEM; + } + dsi->dsi_id = id; + rk_dsi_host_parse_dt(getenv_hex("fdtaddr", 0),dsi); + + screen = calloc(1, sizeof(struct rk_screen)); + if(!screen) { + MIPI_DBG("request struct rk_screen fail!\n"); + } + //rk_fb_get_prmry_screen(screen); + ops = &dsi->ops; + ops->dsi = dsi; + ops->id = DWC_DSI_VERSION, + ops->get_id = rk32_mipi_dsi_get_id, + ops->dsi_send_packet = rk32_mipi_dsi_send_packet; + ops->dsi_read_dcs_packet = rk32_mipi_dsi_read_dcs_packet, + ops->dsi_enable_video_mode = rk32_mipi_dsi_enable_video_mode, + ops->dsi_enable_command_mode = rk32_mipi_dsi_enable_command_mode, + ops->dsi_enable_hs_clk = rk32_mipi_dsi_enable_hs_clk, + ops->dsi_is_active = rk32_mipi_dsi_is_active, + ops->dsi_is_enable= rk32_mipi_dsi_is_enable, + ops->power_up = rk32_mipi_dsi_power_up, + ops->power_down = rk32_mipi_dsi_power_down, + ops->dsi_init = rk_mipi_dsi_init, + + dsi_screen = &dsi->screen; + dsi_screen->type = screen->type = vid->screen_type; + dsi_screen->face = screen->face = vid->lcd_face; + //dsi_screen->lcdc_id = screen->lcdc_id; + //dsi_screen->screen_id = screen->screen_id; + //printf("xjh:vid->vl_freq %d vid->real_freq %d\n",vid->vl_freq, vid->real_freq); + //dsi_screen->pixclock = screen->mode.pixclock = vid->vl_freq *MHZ ; + dsi_screen->pixclock = screen->mode.pixclock = vid->real_freq; + dsi_screen->left_margin = screen->mode.left_margin = vid->vl_hbpd; + dsi_screen->right_margin = screen->mode.right_margin = vid->vl_hfpd; + dsi_screen->hsync_len = screen->mode.hsync_len = vid->vl_hspw; + dsi_screen->upper_margin = screen->mode.upper_margin = vid->vl_vbpd; + dsi_screen->lower_margin = screen->mode.lower_margin = vid->vl_vfpd; + dsi_screen->vsync_len = screen->mode.vsync_len = vid->vl_vspw; + dsi_screen->x_res = screen->mode.xres = vid->vl_width; + dsi_screen->y_res = screen->mode.yres = vid->vl_height; + //dsi_screen->pin_hsync = screen->pin_hsync; + //dsi_screen->pin_vsync = screen->pin_vsync; + //dsi_screen->pin_den = screen->pin_den; + //dsi_screen->pin_dclk = screen->pin_dclk; + dsi_screen->dsi_lane = rk_mipi_get_dsi_lane(); + // dsi_screen->dsi_video_mode = screen->dsi_video_mode; //no sure + dsi_screen->dsi_lane = rk_mipi_get_dsi_lane(); + dsi_screen->hs_tx_clk = rk_mipi_get_dsi_clk(); + dsi_screen->lcdc_id = 1; + dsi->dsi_id = id++;//of_alias_get_id(pdev->dev.of_node, "dsi"); + sprintf(ops->name, "rk_mipi_dsi.%d", dsi->dsi_id); + + ret = rk_mipi_dsi_probe(dsi); + if(ret) { + MIPI_DBG("rk mipi_dsi probe fail!\n"); + MIPI_DBG("%s\n", RK_MIPI_DSI_VERSION_AND_TIME); + } + + if(id == 1){ + rk32_init_phy_mode(dsi_screen->lcdc_id); + //rk_fb_trsm_ops_register(&trsm_dsi_ops, SCREEN_MIPI); + dsi0 = dsi; + }else{ + dsi1 = dsi; + } + //if(vid->screen_type == SCREEN_DUAL_MIPI){ + if( rk_mipi_get_dsi_num() == 2 ){ + if(id==2) + break; + }else + break; + + }while(1); + + rk32_dsi_enable(); + +#if 0 + + int reg = 0; + + // printf("MIPI HOST dump regs\n"); + for(reg=0x0;reg<0xc4;){ + // printf("reg[0x%04x]=0x%08x ",reg, + // __raw_readl(dsi0->host.membase + reg)); + __raw_readl(dsi0->host.membase + reg); + reg+=4; +// if(reg%16 == 0) +// printf("\n"); + } + + MIPI_DBG("rk mipi_dsi probe success!\n"); + MIPI_DBG("%s\n", RK_MIPI_DSI_VERSION_AND_TIME); + #endif + return 0; + +} +#endif +int rk32_mipi_power_down_DDR() +{ + dsi_is_enable(0, 0); + if (rk_mipi_get_dsi_num() ==2) + dsi_is_enable(1, 0); + return 0; +} +EXPORT_SYMBOL(rk32_mipi_power_down_DDR); +int rk32_mipi_power_up_DDR() +{ + dsi_is_enable(0, 0); + if (rk_mipi_get_dsi_num() ==2) + dsi_is_enable(1, 0); + dsi_enable_video_mode(0, 1); + dsi_enable_video_mode(1, 1); + dsi_is_enable(0, 1); + if (rk_mipi_get_dsi_num() ==2) + dsi_is_enable(1, 1); + return 0; +} +EXPORT_SYMBOL(rk32_mipi_power_up_DDR); + +#ifdef CONFIG_MIPI_DSI_LINUX static int rk32_mipi_dsi_probe(struct platform_device *pdev) { int ret = 0; - static id = 0; + static int id = 0; struct dsi *dsi; struct mipi_dsi_ops *ops; struct rk_screen *screen; struct mipi_dsi_screen *dsi_screen; struct resource *res_host; - + dsi = devm_kzalloc(&pdev->dev, sizeof(struct dsi), GFP_KERNEL); if(!dsi) { dev_err(&pdev->dev,"request struct dsi fail!\n"); @@ -1411,6 +1681,12 @@ static int rk32_mipi_dsi_probe(struct platform_device *pdev) } + if(support_uboot_display()){ + clk_prepare_enable(dsi->phy.refclk); + clk_prepare_enable(dsi->dsi_pclk); + clk_prepare_enable(dsi->dsi_pd); + udelay(10); + } dev_info(&pdev->dev,"rk mipi_dsi probe success!\n"); dev_info(&pdev->dev,"%s\n", RK_MIPI_DSI_VERSION_AND_TIME); @@ -1446,3 +1722,4 @@ static void __exit rk32_mipi_dsi_exit(void) platform_driver_unregister(&rk32_mipi_dsi_driver); } module_exit(rk32_mipi_dsi_exit); +#endif diff --git a/drivers/video/rockchip/transmitter/rk32_mipi_dsi.h b/drivers/video/rockchip/transmitter/rk32_mipi_dsi.h index 38568285a749..5504a1cf14c3 100755 --- a/drivers/video/rockchip/transmitter/rk32_mipi_dsi.h +++ b/drivers/video/rockchip/transmitter/rk32_mipi_dsi.h @@ -1,10 +1,12 @@ /* drivers/video/rockchip/transmitter/rk32_mipi_dsi.h */ -#include + #ifndef RK32_MIPI_DSI_H #define RK32_MIPI_DSI_H - +#ifndef CONFIG_RK_3288_DSI_UBOOT +#include +#endif #define MIPI_DSI_HOST_OFFSET 0x1000 //function bits definition register addr | bits | offest @@ -197,11 +199,9 @@ struct dsi_phy { u32 Tpclk; //ps u32 Ttxclkesc; //ps -#ifdef CONFIG_MIPI_DSI_LINUX struct clk *refclk; unsigned long iobase; void __iomem *membase; -#endif u16 prediv; u16 fbdiv; u8 flag; @@ -216,10 +216,8 @@ struct dsi_host { u8 video_mode; u32 clk; u32 irq; -#ifdef CONFIG_MIPI_DSI_LINUX unsigned long iobase; void __iomem *membase; -#endif }; struct dsi { -- 2.34.1