From f5fc2cbd6bcf80cc34c8114007f31d8ffd1d138d Mon Sep 17 00:00:00 2001 From: Jim Laskey Date: Fri, 21 Oct 2005 19:05:19 +0000 Subject: [PATCH] Plugin new subtarget backend into the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23870 91177308-0d34-0410-b5e6-96231b3b80d8 --- Makefile.rules | 4 ++ lib/Target/PowerPC/Makefile | 2 +- lib/Target/PowerPC/PPC.td | 43 +++++++++-------- lib/Target/PowerPC/PPCSubtarget.cpp | 71 ++++++----------------------- lib/Target/Target.td | 2 +- lib/Target/TargetSchedule.td | 4 +- utils/TableGen/TableGen.cpp | 7 +++ 7 files changed, 53 insertions(+), 80 deletions(-) diff --git a/Makefile.rules b/Makefile.rules index 8c550e911da..4b759e6b490 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -1162,6 +1162,10 @@ $(ObjDir)/%GenDAGISel.inc.tmp : %.td $(ObjDir)/.dir $(Echo) "Building $(; -def F64BitRegs : SubtargetFeature<"64bitregs", - "Should 64 bit registers be used">; -def FAltivec : SubtargetFeature<"altivec", - "Should Altivec instructions be used">; -def FGPUL : SubtargetFeature<"gpul", - "Should GPUL instructions be used">; -def FFSQRT : SubtargetFeature<"fsqrt", - "Should the fsqrt instruction be used">; +def Feature64Bit : SubtargetFeature<"64bit", + "Should 64 bit instructions be used">; +def Feature64BitRegs : SubtargetFeature<"64bitregs", + "Should 64 bit registers be used">; +def FeatureAltivec : SubtargetFeature<"altivec", + "Should Altivec instructions be used">; +def FeatureFSqrt : SubtargetFeature<"fsqrt", + "Should the fsqrt instruction be used">; +def FeatureGPUL : SubtargetFeature<"gpul", + "Should GPUL instructions be used">; //===----------------------------------------------------------------------===// -// PowerPC chips sets supported +// PowerPC chips sets supported (sorted by name) // def : Processor<"601", G3Itineraries, []>; def : Processor<"602", G3Itineraries, []>; def : Processor<"603", G3Itineraries, []>; +def : Processor<"603e", G3Itineraries, []>; +def : Processor<"603ev", G3Itineraries, []>; def : Processor<"604", G3Itineraries, []>; +def : Processor<"604e", G3Itineraries, []>; +def : Processor<"620", G3Itineraries, []>; +def : Processor<"7400", G4Itineraries, [FeatureAltivec]>; +def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>; def : Processor<"750", G3Itineraries, []>; -def : Processor<"7400", G4Itineraries, [FAltivec]>; -def : Processor<"g4", G4Itineraries, [FAltivec]>; -def : Processor<"7450", G4PlusItineraries, [FAltivec]>; -def : Processor<"g4+", G4PlusItineraries, [FAltivec]>; def : Processor<"970", G5Itineraries, - [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; + [FeatureAltivec, FeatureGPUL, FeatureFSqrt, + Feature64Bit, Feature64BitRegs]>; +def : Processor<"g4", G4Itineraries, [FeatureAltivec]>; +def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>; def : Processor<"g5", G5Itineraries, - [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; + [FeatureAltivec, FeatureGPUL, FeatureFSqrt, + Feature64Bit, Feature64BitRegs]>; +def : Processor<"generic", G3Itineraries, []>; def PPC : Target { diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index c07b33ec8fe..5393b1d6393 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -16,6 +16,7 @@ #include "llvm/Module.h" #include "llvm/Support/CommandLine.h" #include "llvm/Target/SubtargetFeature.h" +#include "PPCGenSubtarget.inc" using namespace llvm; PPCTargetEnum llvm::PPCTarget = TargetDefault; @@ -29,59 +30,14 @@ namespace llvm { " Enable Darwin codegen"), clEnumValEnd), cl::location(PPCTarget), cl::init(TargetDefault)); -} - -enum PowerPCFeature { - PowerPCFeature64Bit = 1 << 0, - PowerPCFeatureAltivec = 1 << 1, - PowerPCFeatureFSqrt = 1 << 2, - PowerPCFeatureGPUL = 1 << 3, - PowerPCFeature64BRegs = 1 << 4 -}; - -/// Sorted (by key) array of values for CPU subtype. -static const SubtargetFeatureKV PowerPCSubTypeKV[] = { - { "601" , "Select the PowerPC 601 processor", 0 }, - { "602" , "Select the PowerPC 602 processor", 0 }, - { "603" , "Select the PowerPC 603 processor", 0 }, - { "603e" , "Select the PowerPC 603e processor", 0 }, - { "603ev" , "Select the PowerPC 603ev processor", 0 }, - { "604" , "Select the PowerPC 604 processor", 0 }, - { "604e" , "Select the PowerPC 604e processor", 0 }, - { "620" , "Select the PowerPC 620 processor", 0 }, - { "7400" , "Select the PowerPC 7400 (G4) processor", - PowerPCFeatureAltivec }, - { "7450" , "Select the PowerPC 7450 (G4+) processor", - PowerPCFeatureAltivec }, - { "750" , "Select the PowerPC 750 (G3) processor", 0 }, - { "970" , "Select the PowerPC 970 (G5 - GPUL) processor", - PowerPCFeature64Bit | PowerPCFeatureAltivec | - PowerPCFeatureFSqrt | PowerPCFeatureGPUL }, - { "g3" , "Select the PowerPC G3 (750) processor", 0 }, - { "g4" , "Select the PowerPC G4 (7400) processor", - PowerPCFeatureAltivec }, - { "g4+" , "Select the PowerPC G4+ (7450) processor", - PowerPCFeatureAltivec }, - { "g5" , "Select the PowerPC g5 (970 - GPUL) processor", - PowerPCFeature64Bit | PowerPCFeatureAltivec | - PowerPCFeatureFSqrt | PowerPCFeatureGPUL }, - { "generic", "Select instructions for a generic PowerPC processor", 0 } -}; -/// Length of PowerPCSubTypeKV. -static const unsigned PowerPCSubTypeKVSize = sizeof(PowerPCSubTypeKV) - / sizeof(SubtargetFeatureKV); - -/// Sorted (by key) array of values for CPU features. -static SubtargetFeatureKV PowerPCFeatureKV[] = { - { "64bit" , "Should 64 bit instructions be used" , PowerPCFeature64Bit }, - { "64bitregs", "Should 64 bit registers be used" , PowerPCFeature64BRegs }, - { "altivec", "Should Altivec instructions be used" , PowerPCFeatureAltivec }, - { "fsqrt" , "Should the fsqrt instruction be used", PowerPCFeatureFSqrt }, - { "gpul" , "Should GPUL instructions be used" , PowerPCFeatureGPUL } - }; -/// Length of PowerPCFeatureKV. -static const unsigned PowerPCFeatureKVSize = sizeof(PowerPCFeatureKV) +} + +/// Length of FeatureKV. +static const unsigned FeatureKVSize = sizeof(FeatureKV) / sizeof(SubtargetFeatureKV); +/// Length of SubTypeKV. +static const unsigned SubTypeKVSize = sizeof(SubTypeKV) + / sizeof(SubtargetFeatureKV); #if defined(__APPLE__) @@ -131,12 +87,11 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS) #endif uint32_t Bits = SubtargetFeatures::Parse(FS, CPU, - PowerPCSubTypeKV, PowerPCSubTypeKVSize, - PowerPCFeatureKV, PowerPCFeatureKVSize); - IsGigaProcessor = (Bits & PowerPCFeatureGPUL ) != 0; - Is64Bit = (Bits & PowerPCFeature64Bit) != 0; - HasFSQRT = (Bits & PowerPCFeatureFSqrt) != 0; - Has64BitRegs = (Bits & PowerPCFeature64BRegs) != 0; + SubTypeKV, SubTypeKVSize, FeatureKV, FeatureKVSize); + IsGigaProcessor = (Bits & FeatureGPUL ) != 0; + Is64Bit = (Bits & Feature64Bit) != 0; + HasFSQRT = (Bits & FeatureFSqrt) != 0; + Has64BitRegs = (Bits & Feature64BitRegs) != 0; // Set the boolean corresponding to the current target triple, or the default // if one cannot be determined, to true. diff --git a/lib/Target/Target.td b/lib/Target/Target.td index f592fce1805..3ce329f9f76 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -280,7 +280,7 @@ class Processor f> { ProcessorItineraries ProcItin = pi; // Features - list of - list Features; + list Features = f; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/TargetSchedule.td b/lib/Target/TargetSchedule.td index 89c00cdc702..2198c153f7b 100644 --- a/lib/Target/TargetSchedule.td +++ b/lib/Target/TargetSchedule.td @@ -28,8 +28,8 @@ class FuncUnit; // need to complete the stage. Units represent the choice of functional units // that can be used to complete the stage. Eg. IntUnit1, IntUnit2. // -class InstrStage units> { - int Latency = latency; // length of stage in machine cycles +class InstrStage units> { + int Cycles = cycles; // length of stage in machine cycles list Units = units; // choice of functional units } diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp index baa15eb6df4..d356e579125 100644 --- a/utils/TableGen/TableGen.cpp +++ b/utils/TableGen/TableGen.cpp @@ -25,6 +25,7 @@ #include "AsmWriterEmitter.h" #include "InstrSelectorEmitter.h" #include "DAGISelEmitter.h" +#include "SubtargetEmitter.h" #include #include #include @@ -36,6 +37,7 @@ enum ActionType { GenRegisterEnums, GenRegister, GenRegisterHeader, GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector, GenDAGISel, + GenSubtarget, PrintEnums, Parse }; @@ -63,6 +65,8 @@ namespace { "Generate an instruction selector"), clEnumValN(GenDAGISel, "gen-dag-isel", "Generate a DAG instruction selector"), + clEnumValN(GenSubtarget, "gen-subtarget", + "Generate subtarget enumerations"), clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"), clEnumValN(Parse, "parse", @@ -472,6 +476,9 @@ int main(int argc, char **argv) { case GenDAGISel: DAGISelEmitter(Records).run(*Out); break; + case GenSubtarget: + SubtargetEmitter(Records).run(*Out); + break; case PrintEnums: { std::vector Recs = Records.getAllDerivedDefinitions(Class); -- 2.34.1