From f64f17265977efb54e330aae1e72637d75308244 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 23 Jan 2014 16:49:17 +0200 Subject: [PATCH] drm/i915: Fix FBC_FENCE_OFF MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Having a 4 byte register at 0x321b seems unlikely as that's not 4 byte aligned. Since later platforms have more or less the same FBC registers with new names, assume that FBC_FENCE_OFF is at 0x3218 just like DPFC_FENCE_YOFF. This feels like a simple typo in BSpec. 321Bh looks a lot like 3218h after all. Should still be tested on real hardware of course. But I don't have any mobile gen4 systems. Signed-off-by: Ville Syrjälä Acked-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ba0799518e17..8a82c018d874 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1048,7 +1048,7 @@ #define FBC_CTL_IDLE_DEBUG (3<<2) #define FBC_CTL_CPU_FENCE (1<<1) #define FBC_CTL_PLANE(plane) ((plane)<<0) -#define FBC_FENCE_OFF 0x0321b +#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ #define FBC_TAG 0x03300 #define FBC_LL_SIZE (1536) -- 2.34.1