From f66b7b1ff667bbcf9d71f540488b49b38bf72b1d Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Sat, 2 Jun 2012 00:02:45 +0000 Subject: [PATCH] Expand unaligned i16 loads/stores for the Mips backend. This is the first of a series of patches which make changes to the backend to emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157862 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 6ea2692d6f8..d0ea2185e0c 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -292,7 +292,6 @@ bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { switch (SVT) { case MVT::i64: case MVT::i32: - case MVT::i16: return true; case MVT::f32: return Subtarget->hasMips32r2Or64(); -- 2.34.1