From f7609e25903d7a5721d5e54e9b3d0d8d680e9e30 Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Wed, 2 Mar 2016 15:46:58 +0800
Subject: [PATCH] ARM64: dts: rockchip: add i2c node for rk3399

Change-Id: I3a662d25927fc9c2c4f756963f1522c24fce70d6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 126 +++++++++++++++++++++++
 1 file changed, 126 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index f24bb14d2d54..edf99cf0b0e4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -53,6 +53,15 @@
 	#size-cells = <2>;
 
 	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		serial2 = &uart2;
@@ -193,6 +202,97 @@
 		};
 	};
 
+	i2c0: i2c@ff3c0000 {
+		compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+		reg = <0x0 0xff3c0000 0x0 0x1000>;
+		clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
+		clock-names = "i2c", "i2c_sclk";
+		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c0_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@ff110000 {
+		compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+		reg = <0x0 0xff110000 0x0 0x1000>;
+		clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
+		clock-names = "i2c", "i2c_sclk";
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c1_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@ff120000 {
+		compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+		reg = <0x0 0xff120000 0x0 0x1000>;
+		clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
+		clock-names = "i2c", "i2c_sclk";
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c2_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@ff130000 {
+		compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+		reg = <0x0 0xff130000 0x0 0x1000>;
+		clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
+		clock-names = "i2c", "i2c_sclk";
+		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c3_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c5: i2c@ff140000 {
+		compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+		reg = <0x0 0xff140000 0x0 0x1000>;
+		clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
+		clock-names = "i2c", "i2c_sclk";
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c5_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c6: i2c@ff150000 {
+		compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+		reg = <0x0 0xff150000 0x0 0x1000>;
+		clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
+		clock-names = "i2c", "i2c_sclk";
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c6_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c7: i2c@ff160000 {
+		compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+		reg = <0x0 0xff160000 0x0 0x1000>;
+		clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
+		clock-names = "i2c", "i2c_sclk";
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c7_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	uart0: serial@ff180000 {
 		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 		reg = <0x0 0xff180000 0x0 0x100>;
@@ -352,6 +452,32 @@
 		status = "disabled";
 	};
 
+	i2c4: i2c@ff3d0000 {
+		compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+		reg = <0x0 0xff3d0000 0x0 0x1000>;
+		clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
+		clock-names = "i2c", "i2c_sclk";
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c4_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c8: i2c@ff3e0000 {
+		compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
+		reg = <0x0 0xff3e0000 0x0 0x1000>;
+		clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
+		clock-names = "i2c", "i2c_sclk";
+		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c8_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	pmucru: pmu-clock-controller@ff750000 {
 		compatible = "rockchip,rk3399-pmucru";
 		reg = <0x0 0xff750000 0x0 0x1000>;
-- 
2.34.1