From f8835ddba4c311d22c7955c26ff2f439c70eab15 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Fri, 10 Dec 2010 15:11:32 +0800 Subject: [PATCH] rk29: add L2 cache setup --- arch/arm/mm/proc-v7.S | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 3a285218fd15..f5e368dc0912 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -265,6 +265,17 @@ __v7_setup: * NS1 = PRRR[19] = 1 - normal shareable property * NOS = PRRR[24+n] = 1 - not outer shareable */ +#ifdef CONFIG_ARCH_RK29 + /* Setup L2 cache */ + mrc p15, 1, r5, c9, c0, 2 + bic r5, r5, #1 << 29 @ L2 data RAM read multiplexer select: 0 = two cycles + bic r5, r5, #7 << 6 + bic r5, r5, #15 + orr r5, r5, #3 << 6 @ Tag RAM latency: b011 = 4 cycles + orr r5, r5, #4 @ Data RAM latency: b0100 = 5 cycles + mcr p15, 1, r5, c9, c0, 2 +#endif + ldr r5, =0xff0a81a8 @ PRRR ldr r6, =0x40e040e0 @ NMRR mcr p15, 0, r5, c10, c2, 0 @ write PRRR -- 2.34.1