From f945a40f9d61f9ce810d2e290d227f3d41a0a64b Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Sat, 24 Jan 2015 12:58:10 +0000 Subject: [PATCH] [mips] Fix assertion on i128 addition/subtraction on MIPS64 Summary: In addition to the included tests, this fixes test/CodeGen/Generic/i128-addsub.ll on a mips64 host. Reviewers: atanasyan, sagar, vmedic Reviewed By: vmedic Subscribers: sdkie, llvm-commits Differential Revision: http://reviews.llvm.org/D6610 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227003 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips64InstrInfo.td | 10 +++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 32 +++++++-- test/CodeGen/Mips/llvm-ir/add.ll | 95 ++++++++++++++++++++++++++ test/CodeGen/Mips/llvm-ir/sub.ll | 94 +++++++++++++++++++++++++ 4 files changed, 226 insertions(+), 5 deletions(-) create mode 100644 test/CodeGen/Mips/llvm-ir/add.ll create mode 100644 test/CodeGen/Mips/llvm-ir/sub.ll diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index d32ac1b11b8..0e6f436ad06 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -423,6 +423,16 @@ def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// +// Add/sub with carry +def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), + (DSUBu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3; +let AdditionalPredicates = [NotDSP] in { + def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), + (DADDu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3; + def : MipsPat<(addc GPR64:$src, immSExt16:$imm), + (DADDiu GPR64:$src, imm:$imm)>, ISA_MIPS3; +} + // extended loads def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 70963821690..1c0c4b01345 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -240,9 +240,27 @@ SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag, SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1); EVT VT = LHS.getValueType(); - SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops); - SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT, - SDValue(Carry, 0), RHS); + unsigned SltOp = Mips::SLTu; + unsigned AddOp = Mips::ADDu; + if (VT == MVT::i64) { + SltOp = Mips::SLTu64; + AddOp = Mips::DADDu; + } + + SDValue Carry = SDValue(CurDAG->getMachineNode(SltOp, DL, VT, Ops), 0); + if (SltOp == Mips::SLTu64) { + // On 64-bit targets, sltu produces an i64 but our backend currently says + // that SLTu64 produces an i32. We need to fix this in the long run but for + // now, just make the DAG type-correct by asserting the upper bits are zero. + Carry = SDValue(CurDAG->getMachineNode( + Mips::SUBREG_TO_REG, DL, VT, + CurDAG->getTargetConstant(0, VT), Carry, + CurDAG->getTargetConstant(Mips::sub_32, MVT::i32)), + 0); + } + + SDNode *AddCarry = CurDAG->getMachineNode(AddOp, DL, VT, Carry, RHS); + return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(AddCarry, 0)); } @@ -641,7 +659,9 @@ std::pair MipsSEDAGToDAGISel::selectNode(SDNode *Node) { case ISD::SUBE: { SDValue InFlag = Node->getOperand(2); - Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node); + unsigned SubOp = + Node->getValueType(0) == MVT::i64 ? Mips::DSUBu : Mips::SUBu; + Result = selectAddESubE(SubOp, InFlag, InFlag.getOperand(0), DL, Node); return std::make_pair(true, Result); } @@ -649,7 +669,9 @@ std::pair MipsSEDAGToDAGISel::selectNode(SDNode *Node) { if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC. break; SDValue InFlag = Node->getOperand(2); - Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node); + unsigned AddOp = + Node->getValueType(0) == MVT::i64 ? Mips::DADDu : Mips::ADDu; + Result = selectAddESubE(AddOp, InFlag, InFlag.getValue(0), DL, Node); return std::make_pair(true, Result); } diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll new file mode 100644 index 00000000000..abcc0db90af --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -0,0 +1,95 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=M2 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R1-R2 -check-prefix=32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R1-R2 -check-prefix=32R2 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=M4 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R1-R2 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R1-R2 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R6 + +; FIXME: We should be able to have signext on the return value without incurring +; a sign extend. +define i8 @add_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: add_i8: + +; ALL: addu $2, $4, $5 + + %r = add i8 %a, %b + ret i8 %r +} + +; FIXME: We should be able to have signext on the return value without incurring +; a sign extend. +define i16 @add_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: add_i16: + +; ALL: addu $2, $4, $5 + + %r = add i16 %a, %b + ret i16 %r +} + +define signext i32 @add_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: add_i32: + +; ALL: addu $2, $4, $5 + + %r = add i32 %a, %b + ret i32 %r +} + +define signext i64 @add_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: add_i64: + +; ALL-32BIT-DAG: addu [[R1:\$3]], $5, $7 +; ALL-32BIT-DAG: sltu [[T0:\$[0-9]+]], [[R1]], $7 +; ALL-32BIT-DAG: addu [[T1:\$[0-9]+]], [[T0]], $6 +; ALL-32BIT-DAG: addu $2, $4, [[T1]] + +; ALL-64BIT: daddu $2, $4, $5 + + %r = add i64 %a, %b + ret i64 %r +} + +define signext i128 @add_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: add_i128: + +; ALL-32BIT-DAG: lw [[A3:\$[0-9]+]], 28($sp) +; ALL-32BIT-DAG: addu [[T0:\$[0-9]+]], $7, [[A3]] +; ALL-32BIT-DAG: sltu [[T1:\$[0-9]+]], [[T0]], [[A3]] +; ALL-32BIT-DAG: lw [[A2:\$[0-9]+]], 24($sp) +; ALL-32BIT-DAG: addu [[T2:\$[0-9]+]], [[T1]], [[A2]] +; ALL-32BIT-DAG: addu [[T3:\$[0-9]+]], $6, [[T2]] +; ALL-32BIT-DAG: sltu [[T4:\$[0-9]+]], [[T3]], [[A2]] +; ALL-32BIT-DAG: lw [[A1:\$[0-9]+]], 20($sp) +; ALL-32BIT-DAG: addu [[T5:\$[0-9]+]], [[T4]], [[A1]] +; ALL-32BIT-DAG: lw [[A0:\$[0-9]+]], 16($sp) +; ALL-32BIT-DAG: addu [[R1:\$3]], [[R3:\$5]], [[T5]] +; ALL-32BIT-DAG: sltu [[T6:\$[0-9]+]], [[R1]], [[A1]] +; ALL-32BIT-DAG: addu [[T7:\$[0-9]+]], [[T6]], [[A0]] +; ALL-32BIT-DAG: addu $2, [[R2:\$4]], [[T7]] +; ALL-32BIT-DAG: move [[R2]], [[T3]] +; ALL-32BIT-DAG: move [[R3]], [[T0]] + +; ALL-64BIT-DAG: daddu [[R0:\$3]], $5, $7 +; ALL-64BIT-DAG: sltu [[T1:\$[0-9]+]], [[R0]], $7 +; ALL-64BIT-DAG: daddu [[T2:\$[0-9]+]], [[T1]], $6 +; ALL-64BIT-DAG: daddu $2, $4, [[T2]] + + %r = add i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll new file mode 100644 index 00000000000..3b89ff42db8 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/sub.ll @@ -0,0 +1,94 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=M2 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R1-R2 -check-prefix=32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R1-R2 -check-prefix=32R2 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=M4 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R1-R2 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R1-R2 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R6 + +; FIXME: We should be able to have signext on the return value without incurring +; a sign extend. +define i8 @sub_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: sub_i8: + +; ALL: subu $2, $4, $5 + + %r = sub i8 %a, %b + ret i8 %r +} + +; FIXME: We should be able to have signext on the return value without incurring +; a sign extend. +define i16 @sub_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: sub_i16: + +; ALL: subu $2, $4, $5 + + %r = sub i16 %a, %b + ret i16 %r +} + +define signext i32 @sub_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: sub_i32: + +; ALL: subu $2, $4, $5 + + %r = sub i32 %a, %b + ret i32 %r +} + +define signext i64 @sub_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: sub_i64: + +; ALL-32BIT-DAG: subu [[R1:\$3]], $5, $7 +; ALL-32BIT-DAG: sltu [[T0:\$[0-9]+]], $5, $7 +; ALL-32BIT-DAG: addu [[T1:\$[0-9]+]], [[T0]], $6 +; ALL-32BIT-DAG: subu $2, $4, [[T1]] + +; ALL-64BIT: dsubu $2, $4, $5 + + %r = sub i64 %a, %b + ret i64 %r +} + +define signext i128 @sub_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: sub_i128: + +; ALL-32BIT-DAG: lw [[A1:\$[0-9]+]], 20($sp) +; ALL-32BIT-DAG: sltu [[T0:\$[0-9]+]], $5, [[A1]] +; ALL-32BIT-DAG: lw [[A0:\$[0-9]+]], 16($sp) +; ALL-32BIT-DAG: addu [[T1:\$[0-9]+]], [[T0]], [[A0]] +; ALL-32BIT-DAG: lw [[A2:\$[0-9]+]], 24($sp) +; ALL-32BIT-DAG: lw [[A3:\$[0-9]+]], 28($sp) +; ALL-32BIT-DAG: subu [[T2:\$[0-9]+]], $7, [[A3]] +; ALL-32BIT-DAG: subu $2, $4, [[T1]] +; ALL-32BIT-DAG: sltu [[T3:\$[0-9]+]], $6, [[A2]] +; ALL-32BIT-DAG: addu [[T4:\$[0-9]+]], [[T3]], [[A1]] +; ALL-32BIT-DAG: subu $3, $5, [[T4]] +; ALL-32BIT-DAG: sltu [[T5:\$[0-9]+]], $7, [[A3]] +; ALL-32BIT-DAG: addu [[T6:\$[0-9]+]], [[T5]], [[A2]] +; ALL-32BIT-DAG: subu $4, $6, [[T6]] +; ALL-32BIT-DAG: move $5, [[T2]] + +; ALL-64BIT-DAG: dsubu $3, $5, $7 +; ALL-64BIT-DAG: sltu [[T1:\$[0-9]+]], $5, $7 +; ALL-64BIT-DAG: daddu [[T2:\$[0-9]+]], [[T1]], $6 +; ALL-64BIT-DAG: dsubu $2, $4, [[T2]] + + %r = sub i128 %a, %b + ret i128 %r +} -- 2.34.1