From fa7935fcb33436e200fd1e5aa99048ea227d2606 Mon Sep 17 00:00:00 2001 From: Duncan Sands Date: Thu, 30 Oct 2008 19:24:28 +0000 Subject: [PATCH] Shift amounts should have the type given by getShiftAmountTy (i32 in the case of CellSPU). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58449 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/CellSPU/SPUISelLowering.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 8c5b9191409..5671d9d0f35 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -2175,17 +2175,17 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc) ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0) : DAG.getConstant(cast(N0)->getZExtValue(), MVT::i16)); - N1Opc = N1.getValueType().bitsLT(MVT::i16) + N1Opc = N1.getValueType().bitsLT(MVT::i32) ? ISD::ZERO_EXTEND : ISD::TRUNCATE; N1 = (N1.getOpcode() != ISD::Constant - ? DAG.getNode(N1Opc, MVT::i16, N1) + ? DAG.getNode(N1Opc, MVT::i32, N1) : DAG.getConstant(cast(N1)->getZExtValue(), - MVT::i16)); + MVT::i32)); SDValue ExpandArg = DAG.getNode(ISD::OR, MVT::i16, N0, DAG.getNode(ISD::SHL, MVT::i16, - N0, DAG.getConstant(8, MVT::i16))); + N0, DAG.getConstant(8, MVT::i32))); return DAG.getNode(ISD::TRUNCATE, MVT::i8, DAG.getNode(Opc, MVT::i16, ExpandArg, N1)); } @@ -2526,7 +2526,7 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { SDValue N = Op.getOperand(0); SDValue Elt0 = DAG.getConstant(0, MVT::i16); SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16); - SDValue Shift1 = DAG.getConstant(8, MVT::i16); + SDValue Shift1 = DAG.getConstant(8, MVT::i32); SDValue Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N); SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); -- 2.34.1