From fb382752691d74a849996daf77be961ca2cdae97 Mon Sep 17 00:00:00 2001 From: Gary King Date: Wed, 15 Sep 2010 09:49:24 -0700 Subject: [PATCH] [ARM] mm: add memory type for inner-writeback For streaming-style operations (e.g., software rendering of graphics surfaces shared with non-coherent DMA devices), the cost of performing L2 cache maintenance can exceed the benefit of having the larger cache (this is particularly true for OUTER_CACHE configurations like the ARM PL2x0). This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) in the tex remapping tables as an inner-writeback-write-allocate, outer non-cacheable memory type, so that this mapping will be available to clients which will benefit from the reduced L2 maintenance. Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906 Signed-off-by: Gary King --- arch/arm/include/asm/pgtable.h | 3 +++ arch/arm/mm/proc-macros.S | 2 +- arch/arm/mm/proc-v7.S | 6 +++--- arch/arm/mm/proc-xsc3.S | 2 +- arch/arm/mm/proc-xscale.S | 2 +- 5 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index e90b167ea848..73ee18b1a054 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -184,6 +184,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */ #define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */ #define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */ +#define L_PTE_MT_INNER_WB (0x05 << 2) /* 0101 (armv6, armv7) */ #define L_PTE_MT_MASK (0x0f << 2) #ifndef __ASSEMBLY__ @@ -325,6 +326,8 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, #define pgprot_dmacoherent(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED) #endif +#define pgprot_inner_writeback(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_INNER_WB) #define pmd_none(pmd) (!pmd_val(pmd)) #define pmd_present(pmd) (pmd_val(pmd)) diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 7d63beaf9745..6da85e3f0632 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -107,7 +107,7 @@ .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_EXT_TEX(4) | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 750175e95ab0..e0028e5bef13 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -294,11 +294,11 @@ __v7_setup: * NS1 = PRRR[19] = 1 - normal shareable property * NOS = PRRR[24+n] = 1 - not outer shareable */ - ldr r5, =0xff0a81a8 @ PRRR + ldr r5, =0xff0a89a8 @ PRRR #ifdef CONFIG_SMP - ldr r6, =0xc0e0c0e0 @ NMRR + ldr r6, =0xc0e0c4e0 @ NMRR #else - ldr r6, =0x40e040e0 + ldr r6, =0x40e044e0 #endif mcr p15, 0, r5, c10, c2, 0 @ write PRRR mcr p15, 0, r6, c10, c2, 1 @ write NMRR diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 361a51e49030..b5dc61a22bf2 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -373,7 +373,7 @@ cpu_xsc3_mt_table: .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_EXT_TEX(4) | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB (not present?) .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?) .long 0x00 @ unused diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 14075979bcba..69518395e710 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -469,7 +469,7 @@ cpu_xscale_mt_table: .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused -- 2.34.1