From fb50e9e2528a03fc1cfe70d4911e332b218b5c78 Mon Sep 17 00:00:00 2001 From: chenxing Date: Mon, 24 Jun 2013 14:26:39 +0800 Subject: [PATCH] rk3188: fix i2s frac set rate do not effect --- arch/arm/mach-rk3188/clock_data.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c index e5d81416d11a..4616924e5dac 100755 --- a/arch/arm/mach-rk3188/clock_data.c +++ b/arch/arm/mach-rk3188/clock_data.c @@ -1938,12 +1938,19 @@ static struct clk clk_spdif_div = { static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate) { u32 numerator, denominator; + int i = 0; //clk_i2s_div->clk_i2s_pll->gpll/cpll //clk->parent->parent if(frac_div_get_seting(rate, clk->parent->parent->rate, &numerator, &denominator) == 0) { clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1: - cru_writel_frac(numerator << 16 | denominator, clk->clksel_con); + + while (i--) { + cru_writel_frac((numerator - 1) << 16 | denominator, clk->clksel_con); + msleep(1); + cru_writel_frac(numerator << 16 | denominator, clk->clksel_con); + msleep(1); + } CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate); } else { CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name); -- 2.34.1